💻 RTL Design & Verification | IC Tools Development | Digital Systems Enthusiast

I am an ECE student at the University of Michigan with a strong focus on digital IC design, verification, and EDA tool development.
My work spans from RTL implementation and SystemVerilog/UVM verification to EDA automation frameworks and architecture-level design.
I enjoy building projects that bridge circuit design, automation, and real-world applications.

• Hardware Description Languages: Verilog, SystemVerilog, UVM
• EDA & Verification Tools: ModelSim, QuestaSim, Icarus Verilog, GTKWave, Klayout, DRC/LVS/PEX
• EDA Frameworks & Automation: Python-based layout automation, PDK integration
• Computer Architecture: RISC-V ISA extension design & implementation
• Model Optimization & Benchmarking: OpenVINO Runtime, model quantization (INT4/INT8/FP16)
• Programming: Python, C++

A curated collection of RTL design modules and verification environments for common digital interfaces (UART, FIFO, APB, SPI, I2C) and arithmetic units.

• Implemented in Verilog/SystemVerilog with self-written testbenches and waveform outputs.
• Includes UVM-based verification for sequential adder.
• Demonstrates full design-to-verification workflow.

A PDK-agnostic layout automation framework for analog IC design.

• Generates DRC-clean layouts across multiple technology nodes (sky130, gf180).
• Supports natural language to layout conversion and integrates with Klayout for visualization & verification.
• Developed as a Python package for easy deployment in IC design flows.
• Demonstrates EDA tool development and design automation expertise.

A custom RISC-V ISA extension implementing health-related calculations directly in hardware.

• RTL implemented in Verilog, adding instructions for BMI and BMR computation.
• Designed custom I-type and R-type instructions, with memory-mapped user records.
• Demonstrates computer architecture design, custom instruction encoding, and hardware-software co-design.

Python scripts for OpenVINO-based generative AI model inference & benchmarking.

• Adapted from official OpenVINO notebooks for research-driven large-scale image generation.
• Automated batch inference (300 images/run) using prompts from phiyodr/coco2017.
• Evaluated results using IS, CLIP Score, FID, and PickScore.
• While not IC design, demonstrates Python automation, benchmarking, and workflow optimization—skills directly transferable to EDA flow scripting.

• Email: [email protected]
• LinkedIn: linkedin.com/in/erin-xu-a48031294
• GitHub: github.com/ErinXU2004