armv8-r: Add Arm Cortex-R82 non-MPU port

.github/.cSpellWords.txt

@@ -430,6 +430,7 @@ ldrbs
 LDRBS
 LDRNE
 ldsr
+ldxr
 lidt
 LINKR
 LJMP
@@ -505,6 +506,7 @@ movs
 movw
 MOVWF
 movx
+MPIDR
 MPLAB
 MPUCTRL
 MQTT
@@ -779,6 +781,7 @@ SETINTENA
 SETPSW
 SETR
 setvect
+sevl
 SFRC
 SHLL
 SHLR
@@ -809,6 +812,7 @@ STTBRK
 STTDLY
 STTOUT
 STTTO
+stxr
 SVACC
 svcne
 SVDIS

.github/scripts/kernel_checker.py

@@ -118,6 +118,7 @@
     r'.*portable/.*/ARM_CM3_MPU*',
     r'.*portable/.*/ARM_CM4_MPU*',
     r'.*portable/.*/ARM_CM4F_MPU*',
+    r'.*portable/.*/ARM_CR82*',
 ]
 
 KERNEL_HEADER = [

CMakeLists.txt

@@ -87,6 +87,7 @@ if(NOT FREERTOS_PORT)
         " GCC_ARM_CR5                      - Compiler: GCC           Target: ARM Cortex-R5\n"
         " GCC_ARM_CRX_MPU                  - Compiler: GCC           Target: ARM Cortex-Rx with MPU\n"
         " GCC_ARM_CRX_NOGIC                - Compiler: GCC           Target: ARM Cortex-Rx no GIC\n"
+        " GCC_ARM_CR82                     - Compiler: GCC           Target: ARM Cortex-R82\n"
         " GCC_ARM7_AT91FR40008             - Compiler: GCC           Target: ARM7 Atmel AT91R40008\n"
         " GCC_ARM7_AT91SAM7S               - Compiler: GCC           Target: ARM7 Atmel AT91SAM7S\n"
         " GCC_ARM7_LPC2000                 - Compiler: GCC           Target: ARM7 LPC2000\n"

portable/CMakeLists.txt

@@ -218,6 +218,11 @@ add_library(freertos_kernel_port OBJECT
         GCC/ARM_CRx_No_GIC/port.c
         GCC/ARM_CRx_No_GIC/portASM.S>
 
+    # ARMv8-R ports for GCC
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CR82>:
+        GCC/ARM_CR82/port.c
+        GCC/ARM_CR82/portASM.S>
+
     # ARMv4T ARM7TDMI ports for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_AT91FR40008>:
         GCC/ARM7_AT91FR40008/port.c
@@ -964,6 +969,9 @@ target_include_directories(freertos_kernel_port_headers INTERFACE
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CRX_MPU>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CRx_MPU>
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CRX_NOGIC>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CRx_No_GIC>
 
+    # ARMv8-R ports for GCC
+    $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CR82>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM_CR82>
+
     # ARMv4T ARM7TDMI ports for GCC
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_AT91FR40008>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_AT91FR40008>
     $<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_AT91SAM7S>:${CMAKE_CURRENT_LIST_DIR}/GCC/ARM7_AT91SAM7S>

portable/GCC/ARM_CR82/README.md

@@ -0,0 +1,42 @@
+# Arm Cortex-R82 FreeRTOS Kernel Port
+
+# Overview
+
+- This directory contains the FreeRTOS Kernel port for Arm Cortex-R82 based on Armv8-R AArch64 architecture.
+- It provides the portable layer required by the kernel to run on this architecture.
+
+# Supported toolchains
+
+The port is supported and tested on the following toolchains:
+
+  * Arm Compiler for Embedded v6.23 (armclang).
+  * Arm GNU toolchain v14.2.
+
+# Cache Coherency
+
+- This port assumes the hardware or model is fully cache coherent.
+- The port does not perform cache maintenance for shared buffers.
+- If your hardware or model doesn't support full cache coherency, you must handle cache clean/invalidate operations, memory attributes, and any additional barriers in your BSP/application (especially around shared-memory regions).
+
+# SMP Multicore Bring-up
+
+For SMP systems using this port, the application only needs to start the scheduler on the primary core and issue an SVC from each secondary core once they are online. The kernel coordinates the rest and ensures all cores are properly managed.
+
+- Developer-facing summary: call `vTaskStartScheduler()` on the primary core; each secondary core, in its **reset handler**, performs its local init and then issues an SVC (immediate value `106`) to hand off to the kernel. The port will bring all cores under the scheduler.
+
+Primary core flow:
+
+1. Perform core-specific and shared initialization (e.g., set EL1 stack pointer, zero-initialize `.bss`).
+2. Jump to `main()`, create user tasks, optionally pin tasks to specific cores.
+3. Call `vTaskStartScheduler()` which invokes `xPortStartScheduler()`.
+4. `xPortStartScheduler()` configures the primary core tick timer and signals secondary cores that shared init is complete using the `ucPrimaryCoreInitDoneFlag` variable.
+5. Wait until all secondary cores report as brought up.
+6. Once all cores are up, call `vPortRestoreContext()` to schedule the first task on the primary core.
+
+Secondary core flow (to be done in each core’s reset handler):
+
+1. Perform core-specific initialization (e.g., set EL1 stack pointer).
+2. Wait for the primary core's signal that shared initialization is complete (i.e., `ucPrimaryCoreInitDoneFlag` set to 1).
+3. Update `VBAR_EL1` from the boot vector table to the FreeRTOS vector table.
+4. Initialize the GIC redistributor and enable SGIs so interrupts from the primary core are receivable; signal the primary that this secondary is online and ready by setting the its flag in the `ucSecondaryCoresReadyFlags` array.
+5. Issue an SVC with immediate value `106` to enter `FreeRTOS_SWI_Handler`, which will call `vPortRestoreContext()` based on the SVC number to start scheduling on this core.