Pinned Loading

1. FPGA-SpMV-Optimization-ICTP FPGA-SpMV-Optimization-ICTP Public

   FPGA SpMV (CSR/ELL/COO) with Vitis HLS + Vivado on HyperFPGA. Includes HLS IP, block designs, and host scripts. Replicate any method via SpMV_FinalSourceFiles.

   Jupyter Notebook 2

2. NYU-Processor-Design/nyu-processor-design.github.io NYU-Processor-Design/nyu-processor-design.github.io Public

   Verilog 4 69

3. CLUE-FPGA-Porting-CERN CLUE-FPGA-Porting-CERN Public

   FPGA acceleration of CLUE clustering algorithm for the upgraded CMS High Granularity Caloriemeter (HGCAL). Lowering the initiation interval and latency. Adapt CLUE to FPGA through Alpaka.

   SystemVerilog