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Merge pull request #29 from Im-Rises/develop
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Develop
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@Im-Rises
Im-Rises authored Apr 6, 2024
2 parents 0ad8d41 + ed1be51 commit b6bb40b
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Showing 16 changed files with 113 additions and 226 deletions.
8 changes: 4 additions & 4 deletions CMakeLists.txt
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Expand Up @@ -4,7 +4,7 @@ set(CMAKE_CXX_STANDARD 23)
set(CMAKE_CXX_STANDARD_REQUIRED ON)
set(CMAKE_CXX_EXTENSIONS OFF)

set(CHIP8TOPIA_VERSION "1.7.1")
set(CHIP8TOPIA_VERSION "1.8.0")

project("Chip8topia" VERSION ${CHIP8TOPIA_VERSION})
add_subdirectory(${PROJECT_NAME})
Expand All @@ -20,9 +20,9 @@ set(CPACK_PACKAGE_VERSION_MINOR ${PROJECT_VERSION_MINOR})
set(CPACK_PACKAGE_VERSION_PATCH ${PROJECT_VERSION_PATCH})
#set(CPACK_RESOURCE_FILE_LICENSE "${CMAKE_CURRENT_SOURCE_DIR}/LICENSE")
set(CPACK_RESOURCE_FILE_README "${CMAKE_CURRENT_SOURCE_DIR}/README.md")
if(WIN32 OR APPLE)
if (WIN32 OR APPLE)
set(CPACK_GENERATOR "ZIP" CACHE STRING "Generators to support. semi-colon delimited list")
else()
else ()
set(CPACK_GENERATOR "TGZ" CACHE STRING "Generators to support. semi-colon delimited list")
endif()
endif ()
include(CPack)
3 changes: 3 additions & 0 deletions Chip8topia/Chip8Emulator/Chip8CoreBase/Chip8CoreBase.h
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Expand Up @@ -26,6 +26,9 @@ enum class Chip8Frequency : uint32
Freq24000000Hz = 24000000 // 24MHz for Alien-Inv8sion
};

// TODO: make clock private and call it in a non virtual function with a try catch block for safety
// Replace all call to input handler in cpu etc... to a throw exception

// class CpuBase;
class Input;
class Chip8CoreBase
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4 changes: 2 additions & 2 deletions Chip8topia/Chip8Emulator/Chip8CoreBase/Core/CpuBase.cpp
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Expand Up @@ -275,15 +275,15 @@ void CpuBase::RND_Vx_nn(const uint8 x, const uint8 nn)

void CpuBase::SKP_Vx(const uint8 x)
{
if (m_input->isKeyPressed(m_V[x]))
if (m_input->isKeyPressed(m_V[x] & 0xF))
{
skipNextInstruction();
}
}

void CpuBase::SKNP_Vx(const uint8 x)
{
if (!m_input->isKeyPressed(m_V[x]))
if (!m_input->isKeyPressed(m_V[x] & 0xF))
{
skipNextInstruction();
}
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6 changes: 3 additions & 3 deletions Chip8topia/Chip8Emulator/Chip8CoreBase/Core/CpuBase.h
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Expand Up @@ -79,9 +79,9 @@ class CpuBase
void JP_nnn_V0(const uint16 address); // Bnnn
void JP_xnn_Vx(const uint16 address, const uint8 x); // Bxnn
void RND_Vx_nn(const uint8 x, const uint8 nn); // Cxnn
virtual void DRW_Vx_Vy_n(const uint8 x, const uint8 y, const uint8 n) = 0; // Dxyn
virtual void SKP_Vx(const uint8 x); // Ex9E
virtual void SKNP_Vx(const uint8 x); // ExA1
virtual void DRW_Vx_Vy_n(const uint8 x, const uint8 y, const uint8 n) = 0; // DXYN
void SKP_Vx(const uint8 x); // Ex9E
void SKNP_Vx(const uint8 x); // ExA1
void LD_Vx_DT(const uint8 x); // Fx07
void LD_Vx_K(const uint8 x); // Fx0A
void LD_DT_Vx(const uint8 x); // Fx15
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18 changes: 18 additions & 0 deletions Chip8topia/Chip8Emulator/Chip8CoreBase/Core/PpuBase.cpp
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Expand Up @@ -20,6 +20,24 @@ void PpuBase::reset()
}
}

void PpuBase::clearAllPlanes()
{
if (getMode() == PpuMode::LORES)
{
for (unsigned int i = 0; i < PLANE_COUNT; i++)
{
m_loresVideoMemoryPlanes[i].fill(PIXEL_OFF);
}
}
else
{
for (unsigned int i = 0; i < PLANE_COUNT; i++)
{
m_hiresVideoMemoryPlanes[i].fill(PIXEL_OFF);
}
}
}

void PpuBase::scrollDown(uint8 n)
{
}
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1 change: 1 addition & 0 deletions Chip8topia/Chip8Emulator/Chip8CoreBase/Core/PpuBase.h
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Expand Up @@ -37,6 +37,7 @@ class PpuBase

public:
virtual void reset();
void clearAllPlanes();
virtual void clearScreen() = 0;
virtual void scrollDown(uint8 n);
virtual void scrollUp(uint8 n);
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6 changes: 3 additions & 3 deletions Chip8topia/Chip8Emulator/ChipCores/Chip8Core/Core/Chip8Cpu.cpp
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Expand Up @@ -30,10 +30,10 @@ void Chip8Cpu::computeOpcode(const uint16 opcode)
{
case 0x0:
{
switch (opcode & 0x00FF)
switch (opcode & 0x0FFF)
{
case 0xE0: CLS(); break; // 00E0
case 0xEE: RET(); break; // 00EE
case 0x0E0: CLS(); break; // 00E0
case 0x0EE: RET(); break; // 00EE
default: SYS(opcode & 0x0FFF); break; // 0NNN
}
break;
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2 changes: 1 addition & 1 deletion Chip8topia/Chip8Emulator/ChipCores/Chip8Core/Core/Chip8Cpu.h
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Expand Up @@ -23,7 +23,7 @@ class Chip8Cpu final : public CpuBase
void OR_Vx_Vy(const uint8 x, const uint8 y) final; // 8xy1
void AND_Vx_Vy(const uint8 x, const uint8 y) final; // 8xy2
void XOR_Vx_Vy(const uint8 x, const uint8 y) final; // 8xy3
void DRW_Vx_Vy_n(const uint8 x, const uint8 y, const uint8 n) final; // Dxyn
void DRW_Vx_Vy_n(const uint8 x, const uint8 y, const uint8 n) final; // DXYN
void LD_aI_Vx(const uint8 x) final; // Fx55
void LD_Vx_aI(const uint8 x) final; // Fx65

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23 changes: 12 additions & 11 deletions Chip8topia/Chip8Emulator/ChipCores/SChip11Core/Core/SChip11Cpu.cpp
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Expand Up @@ -29,22 +29,23 @@ void SChip11Cpu::computeOpcode(const uint16 opcode)
{
case 0x0:
{
switch (opcode & 0x00FF)
switch (opcode & 0x0FFF)
{
case 0xE0: CLS(); break; // 00E0
case 0xEE: RET(); break; // 00EE
case 0xFB: SCR(nibble1); break; // 00FB
case 0xFC: SCL(nibble1); break; // 00FC
case 0xFD: EXIT(); break; // 00FD
case 0xFE: LORES(); break; // 00FE
case 0xFF: HIRES(); break; // 00FF
case 0x0E0: CLS(); break; // 00E0
case 0x0EE: RET(); break; // 00EE
case 0x0FB: SCR(nibble1); break; // 00FB
case 0x0FC: SCL(nibble1); break; // 00FC
case 0x0FD: EXIT(); break; // 00FD
case 0x0FE: LORES(); break; // 00FE
case 0x0FF: HIRES(); break; // 00FF
default:
{
switch (nibble2)
switch (opcode & 0xFFF0)
{
case 0xC: SCD(nibble1); break; // 00CN
case 0x00C0: SCD(nibble1); break; // 00CN
default: TRIGGER_COMPUTE_OPCODE_ERROR(opcode); break;
}
break;
}
}
break;
Expand Down Expand Up @@ -93,7 +94,7 @@ void SChip11Cpu::computeOpcode(const uint16 opcode)
case 0xA: LD_I_addr(opcode & 0x0FFF); break; // ANNN
case 0xB: JP_xnn_Vx(opcode & 0x0FFF, nibble3); break; // BXNN
case 0xC: RND_Vx_nn(nibble3, opcode & 0x00FF); break; // CXNN
case 0xD: DRW_Vx_Vy_n(nibble3, nibble2, nibble1); break; // Dxyn
case 0xD: DRW_Vx_Vy_n(nibble3, nibble2, nibble1); break; // DXYN
case 0xE:
{
switch (opcode & 0x00FF)
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2 changes: 1 addition & 1 deletion Chip8topia/Chip8Emulator/ChipCores/SChip11Core/Core/SChip11Cpu.h
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Expand Up @@ -27,7 +27,7 @@ class SChip11Cpu final : public CpuBase
void SCL(const uint8 n) final; // 00FC
void SHR_Vx_Vy(const uint8 x, const uint8 y) final; // 8xy6
void SHL_Vx_Vy(const uint8 x, const uint8 y) final; // 8xyE
void DRW_Vx_Vy_n(const uint8 x, const uint8 y, const uint8 n) final; // Dxyn
void DRW_Vx_Vy_n(const uint8 x, const uint8 y, const uint8 n) final; // DXYN
void LD_R_Vx(const uint8 x) final; // Fx75
void LD_Vx_R(const uint8 x) final; // Fx85

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143 changes: 14 additions & 129 deletions Chip8topia/Chip8Emulator/ChipCores/SchipCCore/Core/SChipCCpu.cpp
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Expand Up @@ -27,22 +27,23 @@ void SChipCCpu::computeOpcode(const uint16 opcode)
{
case 0x0:
{
switch (opcode & 0x00FF)
switch (opcode & 0x0FFF)
{
case 0xE0: CLS(); break; // 00E0
case 0xEE: RET(); break; // 00EE
case 0xFB: SCR(nibble1); break; // 00FB
case 0xFC: SCL(nibble1); break; // 00FC
case 0xFD: EXIT(); break; // 00FD
case 0xFE: LORES(); break; // 00FE
case 0xFF: HIRES(); break; // 00FF
case 0x0E0: CLS(); break; // 00E0
case 0x0EE: RET(); break; // 00EE
case 0x0FB: SCR(nibble1); break; // 00FB
case 0x0FC: SCL(nibble1); break; // 00FC
case 0x0FD: EXIT(); break; // 00FD
case 0x0FE: LORES(); break; // 00FE
case 0x0FF: HIRES(); break; // 00FF
default:
{
switch (nibble2)
switch (opcode & 0xFFF0)
{
case 0xC: SCD(nibble1); break; // 00CN
case 0x00C0: SCD(nibble1); break; // 00CN
default: TRIGGER_COMPUTE_OPCODE_ERROR(opcode); break;
}
break;
}
}
break;
Expand Down Expand Up @@ -91,7 +92,7 @@ void SChipCCpu::computeOpcode(const uint16 opcode)
case 0xA: LD_I_addr(opcode & 0x0FFF); break; // ANNN
case 0xB: JP_nnn_V0(opcode & 0x0FFF); break; // BNNN
case 0xC: RND_Vx_nn(nibble3, opcode & 0x00FF); break; // CXNN
case 0xD: DRW_Vx_Vy_n(nibble3, nibble2, nibble1); break; // Dxyn
case 0xD: DRW_Vx_Vy_n(nibble3, nibble2, nibble1); break; // DXYN
case 0xE:
{
switch (opcode & 0x00FF)
Expand Down Expand Up @@ -123,122 +124,6 @@ void SChipCCpu::computeOpcode(const uint16 opcode)
}
default: TRIGGER_COMPUTE_OPCODE_ERROR(opcode); break;
}

// const uint8 nibble4 = (opcode & 0xF000) >> 12;
// const uint8 nibble3 = (opcode & 0x0F00) >> 8;
// const uint8 nibble2 = (opcode & 0x00F0) >> 4;
// const uint8 nibble1 = (opcode & 0x000F);
//
// switch (nibble4)
// {
// case 0x0:
// {
// switch (nibble2)
// {
// case 0xC: SCD(nibble1); break; // 00CN
// case 0xE:
// {
// switch (nibble1)
// {
// case 0x0: CLS(); break; // 00E0
// case 0xE: RET(); break; // 00EE
// }
// break;
// }
// case 0xF:
// {
// switch (nibble1)
// {
// case 0xB: SCR(nibble1); break; // 00FB
// case 0xC: SCL(nibble1); break; // 00FC
// case 0xD: EXIT(); break; // 00FD
// case 0xE: LORES(); break; // 00FE
// case 0xF: HIRES(); break; // 00FF
// }
// break;
// }
// }
// break;
// }
//
// case 0x1: JP_addr(opcode & 0x0FFF); break; // 1NNN
// case 0x2: CALL_addr(opcode & 0x0FFF); break; // 2NNN
// case 0x3: SE_Vx_nn(nibble3, opcode & 0x00FF); break; // 3XNN
// case 0x4: SNE_Vx_nn(nibble3, opcode & 0x00FF); break; // 4XNN
// case 0x5: SE_Vx_Vy(nibble3, nibble2); break; // 5XY0
// case 0x6: LD_Vx_nn(nibble3, opcode & 0x00FF); break; // 6XNN
// case 0x7: ADD_Vx_nn(nibble3, opcode & 0x00FF); break; // 7XNN
// case 0x8:
// {
// switch (nibble1)
// {
// case 0x0: LD_Vx_Vy(nibble3, nibble2); break; // 8XY0
// case 0x1: OR_Vx_Vy(nibble3, nibble2); break; // 8XY1
// case 0x2: AND_Vx_Vy(nibble3, nibble2); break; // 8XY2
// case 0x3: XOR_Vx_Vy(nibble3, nibble2); break; // 8XY3
// case 0x4: ADD_Vx_Vy(nibble3, nibble2); break; // 8XY4
// case 0x5: SUB_Vx_Vy(nibble3, nibble2); break; // 8XY5
// case 0x6: SHR_Vx_Vy(nibble3, nibble2); break; // 8XY6
// case 0x7: SUBN_Vx_Vy(nibble3, nibble2); break; // 8XY7
// case 0xE: SHL_Vx_Vy(nibble3, nibble2); break; // 8XYE
// }
// break;
// }
// case 0x9: SNE_Vx_Vy(nibble3, nibble2); break; // 9XY0
// case 0xA: LD_I_addr(opcode & 0x0FFF); break; // ANNN
// case 0xB: JP_nnn_V0(opcode & 0x0FFF); break; // BNNN
// case 0xC: RND_Vx_nn(nibble3, opcode & 0x00FF); break; // CXNN
// case 0xD: DRW_Vx_Vy_n(nibble3, nibble2, nibble1); break; // Dxyn
// case 0xE:
// {
// switch (nibble1)
// {
// case 0xE: SKP_Vx(nibble3); break; // EX9E
// case 0x1: SKNP_Vx(nibble3); break; // EXA1
// }
// break;
// }
// case 0xF:
// {
// switch (nibble2)
// {
// case 0x0:
// {
// switch (nibble1)
// {
// case 0x7: LD_Vx_DT(nibble3); break; // FX07
// case 0xA: LD_Vx_K(nibble3); break; // FX0A
// }
// break;
// }
// case 0x1:
// {
// switch (nibble1)
// {
// case 0x5: LD_DT_Vx(nibble3); break; // FX15
// case 0x8: LD_ST_Vx(nibble3); break; // FX18
// case 0xE: ADD_I_Vx(nibble3); break; // FX1E
// }
// break;
// }
// case 0x2: LD_F_Vx(nibble3); break; // FX29
// case 0x3:
// {
// switch (nibble1)
// {
// case 0x0: LD_HF_Vx(nibble3); break; // FX30
// case 0x3: LD_B_Vx(nibble3); break; // FX33
// }
// break;
// }
// case 0x5: LD_aI_Vx(nibble3); break; // FX55
// case 0x6: LD_Vx_aI(nibble3); break; // FX65
// case 0x7: LD_R_Vx(nibble3); break; // FX75
// case 0x8: LD_Vx_R(nibble3); break; // FX85
// }
// break;
// }
// }
}

void SChipCCpu::SCD(const uint8 n)
Expand All @@ -258,12 +143,12 @@ void SChipCCpu::SCL(const uint8 n)

void SChipCCpu::LORES()
{
m_ppu->clearScreen();
m_ppu->clearAllPlanes();
CpuBase::LORES();
}
void SChipCCpu::HIRES()
{
m_ppu->clearScreen();
m_ppu->clearAllPlanes();
CpuBase::HIRES();
}

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2 changes: 1 addition & 1 deletion Chip8topia/Chip8Emulator/ChipCores/SchipCCore/Core/SChipCCpu.h
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Expand Up @@ -27,7 +27,7 @@ class SChipCCpu final : public CpuBase
void OR_Vx_Vy(const uint8 x, const uint8 y) final; // 8xy1
void AND_Vx_Vy(const uint8 x, const uint8 y) final; // 8xy2
void XOR_Vx_Vy(const uint8 x, const uint8 y) final; // 8xy3
void DRW_Vx_Vy_n(const uint8 x, const uint8 y, const uint8 n) final; // Dxyn
void DRW_Vx_Vy_n(const uint8 x, const uint8 y, const uint8 n) final; // DXYN
void LD_aI_Vx(const uint8 x) final; // Fx55
void LD_Vx_aI(const uint8 x) final; // Fx65
void LD_R_Vx(const uint8 x) final; // Fx75
Expand Down
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