🔄 Circular FIFO Buffer (VHDL)

A modular and efficient Circular FIFO Buffer implemented in VHDL, designed with scalability, configurability, and simulation support in mind.
This project demonstrates a clean architectural separation between the controller and memory elements, and includes a self-checking testbench for easy validation in ModelSim or other HDL simulators.

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🧩 Project Overview

This FIFO (First-In-First-Out) buffer is implemented as a circular queue using VHDL.
It supports concurrent read and write operations with proper control logic to handle full and empty conditions, making it suitable for data-streaming and buffering applications in FPGA or ASIC designs.

Key Features

• Fully synthesizable and parameterized architecture
• Modular structure (Controller + Register File)
• Circular addressing with automatic wrap-around
• Status flags: FULL, EMPTY, and DATA_VALID
• Compatible with ModelSim / QuestaSim simulation flow
• Clean package-based design (FIFO_BUFFER_PKG.vhd) for reusability

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🚀 Getting Started

1. Clone the Repository

git clone https://github.com/KyloReneo/FIFO_BUFFER.git

cd FIFO_BUFFER

2. Open in ModelSim

Run the included TCL script to compile and simulate the project:

vsim -do compile.tcl

3. Simulate the Testbench

vsim work.TB_FIFO_BUFFER
run -all

4. (Optional) View Waveforms

view wave
add wave *

You can modify constants in FIFO_BUFFER_PKG.vhd to change FIFO depth and data width before simulation.

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📂 Repository Structure

FIFO_BUFFER/
├── compile.tcl               # TCL script for ModelSim compilation
├── FIFO_BUFFER.vhd           # Top-level FIFO entity
├── TB_FIFO_BUFFER.vhd        # Testbench for functional verification
├── src/
│   ├── modules/
│   │   ├── FIFO_CONTROLLER.vhd   # Handles pointer logic and status flags
│   │   └── REGISTER_FILE.vhd     # Memory storage array for data
│   └── packages/
│       └── FIFO_BUFFER_PKG.vhd   # Contains constants, types, and generics
├── modelsim.ini              # ModelSim simulation configuration
├── FIFO_BUFFER.mpf           # ModelSim project file
└── work/                     # Simulation artifacts (auto-generated)

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⚙️ Design Description

The FIFO is divided into two main components:

1. FIFO_CONTROLLER

• Manages write/read pointers
• Detects full and empty states
• Generates control signals for data flow

2. REGISTER_FILE

• Implements data storage using an array of registers
• Indexed by the controller pointers
• Provides synchronous read/write access

3. Top-Level (FIFO_BUFFER.vhd)

• Instantiates both submodules
• Interfaces with the external system
• Uses types and constants defined in the package

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🧪 Testbench

The TB_FIFO_BUFFER.vhd file provides a simulation testbench that:

• Applies random or sequential write/read patterns
• Verifies data integrity through the FIFO
• Displays flag transitions (FULL, EMPTY) during simulation
• Can be run directly in ModelSim or QuestaSim

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🔧 Parameters

You can modify FIFO parameters (like depth, data width) in FIFO_BUFFER_PKG.vhd:

constant FIFO_DEPTH : integer := 16;
constant DATA_WIDTH : integer := 8;

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📜 License

This project is licensed under the GNU General Public License v3.0 (GPL-3.0) so feel free to modify it under the terms of this license..

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👨‍💻 Author

SaEeD
📧 saeedderayat2000@gmail.com 💡 Open to collaboration and feedback!

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⭐ Acknowledgements

Inspired by classical hardware FIFO architectures and optimized for modern HDL simulation and synthesis tools.