Welcome to the SystemsGenesis CSAW 2023 AI Hardware Attack Challenge repository!
This repository contains the digital designs created by the SystemsGenesys team for the CSAW 2023 AI Hardware Attack Challenge. The challenge focused on creating hardware-based malware using Large Language Models (LLMs), with ChatGPT4 as the chosen LLM.
If you'd like to explore our projects, please refer to the respective project folders for detailed instructions on how to use and test them.
Feel free to reach out to us if you have any questions!
Happy hacking!
We've developed three different hardware malware projects using SystemVerilog and various techniques:
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UART Peripheral Denial-of-Service (DoS) Malware
- Location: Project Folder
- Description: This project features a Denial-of-Service malware targeting a UART peripheral.
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Wishbone Bus Peripheral Denial-of-Service (DoS) Malware
- Location: Project Folder
- Description: This project showcases a Denial-of-Service malware designed for a Wishbone bus peripheral.
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Caravel Wishbone Bus Peripheral Denial-of-Service (DoS) Malware
- Location: Project Folder
- Description: This project showcases a Denial-of-Service malware designed for the SPI Wishbone back-door state machine.
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AES Encryption/Decryption IP Block Information Leakage Malware
- Location: Project Folder
- Description: In this project, we've created malware to leak sensitive information (key) from an AES encryption/decryption IP block.
We utilized the Chain Of Thought (CoT) technique for prompt engineering and also employed the recipe and persona prompt pattern to interact with the LLM effectively.
More details about the techniques, prompts and any other details about the projects:
- Location: Project Folder
To ensure the functionality and security of our designs, we used EDAplayground for testing and verification.
/ip: Contains any IP blocks used in reference for each project./rtl: Contains the SystemVerilog code for each project./test: Includes testbenches for validating project functionality./simulation: Stores simulation files./synthesis: For synthesis-related files.
All projects in this repository are open source under the Apache License.
- University: International Hellenic University
- Lab: Web Engineering and Intelligent Systems Lab (wesis) s
Disclaimer: This repository is intended for educational and research purposes only. Malicious use of the provided designs is strictly prohibited.