🚀 Project_Processor: 5-Stage Pipelined MIPS Processor

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🌟 Overview

This project implements a 5-stage pipelined MIPS processor in Verilog as part of the CUFE CMP3010 [Computer Architecture] course. The processor supports instruction fetch, decode, execute, memory access, and write-back stages, with hazard detection and control logic for robust pipelined execution.

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🧠 Design Philosophy

• Modular Design: Each pipeline stage is implemented as a separate module for clarity and extensibility.
• Hazard Handling: Includes dedicated units for hazard detection and jump/branch control to ensure correct instruction flow.
• Testability: Testbenches are provided for individual modules and full integration.
• Memory Management: Separate modules for instruction and data memory, supporting read/write operations.

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🏗️ Architecture & Pipeline Stages

1. Fetch (Fetch.v): Retrieves instructions from memory, increments the program counter, and handles branching.
2. Decode (Decode.v, Decode2.v): Decodes instructions, generates control signals, and reads register values.
3. Execute (ALU.v, FU.v): Performs arithmetic and logic operations, sets flags, and handles forwarding.
4. Memory (Memory.v, Data_Memory.v): Accesses data memory for load/store instructions.
5. Write Back (WriteBack.v): Writes results back to registers.

Hazard Detection:

• HazardDetectionUnit.v stalls pipeline stages when data hazards are detected.

Jump/Branch Control:

• JDU.v manages jump instructions and flushes pipeline stages as needed.

Intermediate Buffers:

• intermediate_buffers.v implements pipeline registers between stages.

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📁 File Explanations

File/Folder	Purpose & Details
MIPS_phase_3.v	Top-level processor module, connects all stages
Fetch.v	Instruction fetch logic
Decode.v, Decode2.v	Instruction decode and control unit
ALU.v	Arithmetic Logic Unit
FU.v	Forwarding Unit for data hazards
HazardDetectionUnit.v	Hazard detection logic
JDU.v	Jump/branch control unit
Memory.v, Data_Memory.v	Memory modules for instructions and data
WriteBack.v	Write-back stage logic
intermediate_buffers.v	Pipeline registers between stages
testFetch.v, testInteg.v, Data_Memory_tb.v	Testbenches for simulation
tc_two_operands.asm	Example assembly program for testing
units.drawio	Pipeline architecture diagram (add image here)
README.md	Project documentation

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✨ Features

• 5-stage pipelined architecture
• Data and control hazard detection and resolution
• Forwarding and stalling logic
• Branch and jump support
• Modular, extensible Verilog codebase
• Testbenches for validation

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🛠️ Technologies Used

• Verilog HDL
• ModelSim / Vivado / Icarus Verilog (for simulation)
• Draw.io (for architecture diagrams)
• Assembly (for test programs)

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📦 Getting Started

1. Clone the repository:

   git clone https://github.com/<your-username>/Project_Processor-MIPS_phase3_new.git
   cd Project_Processor-MIPS_phase3_new

2. Open the project in your preferred Verilog simulator (ModelSim, Vivado, etc.)
3. Simulate the top-level module (MIPS_phase_3.v) and testbenches.
4. Edit tc_two_operands.asm to test custom instruction sequences.

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💡 Example Simulation Flow

// Example: Simulating the Fetch stage
module testFetch();
    reg clk, reset;
    wire [15:0] instruction;
    reg [31:0] pcin;
    wire [31:0] pcout;

    Fetch f(pcin, pcout, instruction, clk, reset);

    initial begin
        clk = 0;
        reset = 0;
        pcin = 0;
        forever #50 clk = ~clk;
    end

    always @(posedge clk) begin
        pcin = pcout;
    end
endmodule

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📝 Notes & Design Choices

• Pipeline Buffers: Used to separate stages and maintain instruction/data flow.
• Hazard Detection: Ensures correct execution order and prevents data corruption.
• Forwarding Unit: Minimizes stalls by forwarding data between stages.
• Branch/Jump Logic: Handles control flow changes efficiently.
• Memory Modules: Support large address spaces and efficient access.

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📂 File Structure

Project_Processor-MIPS_phase3_new/
│
├── MIPS_phase_3.v
├── Fetch.v
├── Decode.v
├── Decode2.v
├── ALU.v
├── FU.v
├── HazardDetectionUnit.v
├── JDU.v
├── Memory.v
├── Data_Memory.v
├── WriteBack.v
├── intermediate_buffers.v
├── testFetch.v
├── testInteg.v
├── Data_Memory_tb.v
├── tc_two_operands.asm
├── units.drawio
├── README.md
└── ...

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🤝 Contributing

Contributions, suggestions, and feedback are welcome! Feel free to fork the repo, open issues, or submit pull requests.

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📝 License

• Licensed under the MIT License

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Design. Simulate. Learn. 🚀