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gpunetio_verbs_put_bw: pipeline PUT completions with a fixed in-flight window - #14

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gpunetio_verbs_put_bw: pipeline PUT completions with a fixed in-flight window#14
foraxe wants to merge 2 commits into
NVIDIA-DOCA:mainfrom
foraxe:p0/put-window

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@foraxe

@foraxe foraxe commented Aug 2, 2026

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Summary

Remove the per-PUT completion stall in the GPU-initiated PUT bandwidth sample by keeping a small,
fixed FIFO window of PUTs outstanding per producer thread.

Motivation

The current kernel submits one PUT and immediately polls its completion. On GB200, this serializes
submission behind completion latency and leaves the SQ underfilled, especially for one-producer
experiments.

Before:
post 0 -> poll 0 -> post 1 -> poll 1 -> post 2 -> poll 2

After, depth 4:
post 0,1,2,3 -> poll 0 / post 4 -> poll 1 / post 5 -> ... -> drain
                  ^ fixed FIFO completion window keeps the SQ populated

Implementation

  • Add -w for fixed completion-window depths 1, 2, 4, and 8.
  • Add -t to control the total producer thread count.
  • Keep terminal tickets in scalar registers, poll the oldest ticket, refill that slot, and drain
    exactly at the end.
  • Preserve the original depth-one kernel path as the default.
  • Reject invalid launch geometry before resource creation.
  • Exchange a versioned workload descriptor and use exact-length socket I/O so both peers agree on
    producer geometry before RDMA metadata exchange. Both peers must use this control protocol.

The depth-four SM100 specialization uses 60 registers with zero stack, local memory, shared memory,
or barriers.

GB200 results

Configuration: GPU0 (08:01:00.0), mlx5_0, RoCEv2 GID 3, direct GPU doorbell, THREAD scope,
one CUDA thread, 8192 PUTs, three repetitions per final cell.

Message size Depth 1 Depth 4 Gain
4 KiB 3.658 Gbps 5.603 Gbps +53.2%
64 KiB 50.632 Gbps 89.657 Gbps +77.1%
1 MiB 287.670 Gbps 392.902 Gbps +36.6%

The 1 MiB depth-four result ranged from 392.892 to 392.915 Gbps. The one-thread path reaches
100.85% of the official default path's 1 MiB throughput while launching one partial warp instead
of 16 full warps.

Validation

  • make -j16 CUDA_ARCH=100: passed for the library and all examples.
  • Every final server run passed full-buffer payload validation.
  • Review regression after protocol hardening: 5.604 / 89.656 / 392.916 Gbps at 4 KiB / 64 KiB /
    1 MiB with full validation.
  • Server -t 1 versus client -t 2: both peers exited nonzero before QP connection.
  • WARP scope with 32 threads and depth 1 passed validation.
  • Invalid depth, zero threads, queue overflow, and invalid WARP geometry are rejected.

Scope

This patch addresses completion-depth starvation. It does not batch WQE reservation, ready-frontier
publication, doorbells, or CQEs; those are intentionally left for a separate follow-up.

Base: NVIDIA main at df883ff6b5b52f793a7a7eea434485e38891c12f.

@foraxe

foraxe commented Aug 2, 2026

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Stage 1 of the performance plan in RFC #15.

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