Issues

• (Docs): Fix Hex Formatting in Module related Docs

  enhancement
  NYU-Processor-Design/nyu-core#168 · Filter by author ShinyMiraidon opened on Apr 4, 2024
  

• Connection Module: Branching Control

  needs to be connected
  NYU-Processor-Design/nyu-core#134 · Filter by author ShinyMiraidon opened on Nov 29, 2023

• Task: Confirm full ISA functionality

  todo
  NYU-Processor-Design/nyu-core#130 · Filter by author ShinyMiraidon opened on Nov 21, 2023

• Task: Connect Caches to AMBA for memory access

  todo
  NYU-Processor-Design/nyu-core#129 · Filter by author ShinyMiraidon opened on Nov 21, 2023

• Connection Module: MEM

  needs to be implemented
  NYU-Processor-Design/nyu-core#124 · Filter by author ShinyMiraidon opened on Nov 20, 2023
  1

• Connection Module: EX

  needs to be connected
  NYU-Processor-Design/nyu-core#123 · Filter by author ShinyMiraidon opened on Nov 20, 2023

• Connection Module: ID

  needs to be implemented
  NYU-Processor-Design/nyu-core#122 · Filter by author ShinyMiraidon opened on Nov 20, 2023

• Connection Module: IF

  needs to be outlined
  NYU-Processor-Design/nyu-core#121 · Filter by author ShinyMiraidon opened on Nov 20, 2023
  2

• Interface: Flush Bus

  on hold
  NYU-Processor-Design/nyu-core#103 · Filter by author ShinyMiraidon opened on Oct 18, 2023

• Task: Figure out cache clock timing

  todo
  NYU-Processor-Design/nyu-core#97 · Filter by author ShinyMiraidon opened on Oct 16, 2023
  1

• Connection Module: Data Cache

  needs to be implemented
  NYU-Processor-Design/nyu-core#95 · Filter by author ShinyMiraidon opened on Oct 16, 2023
  1

• Connection Module: Instruction Cache

  needs to be outlined
  NYU-Processor-Design/nyu-core#94 · Filter by author ShinyMiraidon opened on Oct 16, 2023
  1

  

• Interface: Instruction Cache Bus

  on hold
  NYU-Processor-Design/nyu-core#93 · Filter by author ShinyMiraidon opened on Oct 16, 2023

• Interface: Source Register Data

  on hold
  NYU-Processor-Design/nyu-core#92 · Filter by author ShinyMiraidon opened on Oct 16, 2023

• Interface: Source Register Numbers

  on hold
  NYU-Processor-Design/nyu-core#91 · Filter by author ShinyMiraidon opened on Oct 16, 2023

• Interface: Destination Register Info

  on hold
  NYU-Processor-Design/nyu-core#90 · Filter by author ShinyMiraidon opened on Oct 16, 2023

• Interface: ALU Operands

  on hold
  NYU-Processor-Design/nyu-core#88 · Filter by author ShinyMiraidon opened on Oct 13, 2023

• Task: Implement all connection modules

  in progress
  NYU-Processor-Design/nyu-core#80 · Filter by author ShinyMiraidon opened on Oct 5, 2023

• Task: Implement all interfaces

  on hold
  NYU-Processor-Design/nyu-core#79 · Filter by author ShinyMiraidon opened on Oct 5, 2023

• Task: Implement all modules

  in progress
  NYU-Processor-Design/nyu-core#78 · Filter by author ShinyMiraidon opened on Oct 5, 2023

• Task: Finalize Cache Designs

  in progress
  NYU-Processor-Design/nyu-core#77 · Filter by author ShinyMiraidon opened on Oct 5, 2023

• Task: Outline all connection modules

  in progress
  NYU-Processor-Design/nyu-core#76 · Filter by author ShinyMiraidon opened on Oct 5, 2023

• Task: Outline all interfaces

  on hold
  NYU-Processor-Design/nyu-core#75 · Filter by author ShinyMiraidon opened on Oct 5, 2023

• Task: Outline all modules

  in progress
  NYU-Processor-Design/nyu-core#74 · Filter by author ShinyMiraidon opened on Oct 5, 2023

• Task: Create issues for every interface

  on hold
  NYU-Processor-Design/nyu-core#72 · Filter by author ShinyMiraidon opened on Oct 5, 2023