[Schema] Extention for debugger RTT

tools/projmgr/schemas/common.schema.json

@@ -2271,13 +2271,59 @@
         "dbgconf":         { "type": "string", "description": "Debugger configuration file (pinout, trace)." },
         "start-pname":     { "type": "string", "description": "Debugger connects at start to this processor." },
         "gdbserver":       { "$ref": "#/definitions/GdbServersType" },
-        "telnet":          { "$ref": "#/definitions/TelnetOptionsType" }
+        "telnet":          { "$ref": "#/definitions/TelnetOptionsType" },
+        "rtt":             { "$ref": "#/definitions/RttOptionsType" }
       },
       "additionalProperties": true,
       "required": ["name"]
     },
+    "RttOptionsType": {
+      "title": "rtt:\nDocumentation: https://open-cmsis-pack.github.io/cmsis-toolbox/pyOCD-Debugger/#rtt",
+      "description": "Configuration for RTT features.",
+      "type": "array",
+      "uniqueItems": true,
+      "items": { "$ref": "#/definitions/RttOptionType" }
+    },
+    "RttOptionType": {
+      "type": "object",
+      "properties": {
+        "pname":         { "type": "string", "description": "Name of the processor (only required for multi-core systems)." },
+        "control-block": { "$ref": "#/definitions/RttControlBlockType" },
+        "channel":       { "$ref": "#/definitions/RttChannelsType" }
+      },
+      "additionalProperties": false,
+      "required": ["channel"]
+    },
+    "RttControlBlockType": {
+      "title": "control-block:\nDocumentation: https://open-cmsis-pack.github.io/cmsis-toolbox/pyOCD-Debugger/#control-block",
+      "description": "Configuration for RTT control block features.",
+      "type": "object",
+      "properties": {
+        "auto-detect": { "type": "boolean", "description": "Scan default memory regions for the RTT control block signature (true or false)." },
+        "address":     { "type": "number", "description": "Control block address, acts as scan start address." },
+        "size":        { "type": "number", "description": "Scan length in bytes." }
+      },
+      "additionalProperties": false
+    },
+    "RttChannelsType": {
+      "title": "channel:\nDocumentation: https://open-cmsis-pack.github.io/cmsis-toolbox/pyOCD-Debugger/#channel",
+      "description": "Configuration for RTT features.",
+      "type": "array",
+      "uniqueItems": true,
+      "items": { "$ref": "#/definitions/RttChannelType" }
+    },
+    "RttChannelType": {
+      "type": "object",
+      "properties": {
+        "number":   { "type": "number", "description": "RTT channel number." },
+        "mode":     { "enum": [ "stdio", "server", "systemview", "systemview-server" ], "description": "RTT channel mode." },
+        "port":     { "type": "number", "description": "TCP port number (required for server and systemview-server)." }
+      },
+      "additionalProperties": false,
+      "required": [ "number", "mode" ]
+    },
     "TelnetOptionsType": {
-      "title": "telnet:\nDocumentation: https://open-cmsis-pack.github.io/cmsis-toolbox/YML-Input-Format/#telnet-for-pyocd",
+      "title": "telnet:\nDocumentation: https://open-cmsis-pack.github.io/cmsis-toolbox/pyOCD-Debugger/#telnet",
       "description": "Telnet port for connecting remote tools.",
       "type": "array",
       "uniqueItems": true,

tools/projmgr/test/data/TestRunDebug/invalid_telnet_rtt_schema.cbuild-run.yml

@@ -0,0 +1,259 @@
+cbuild-run:
+  generated-by: csolution version 0.0.0
+  solution: ../solution.csolution.yml
+  target-type: CM0
+  target-set: <default>
+  compiler: AC6
+  board: Keil::RteTest Dummy board:1.2.3
+  board-pack: ARM::RteTest_DFP@0.2.0
+  board-pack-path: ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.2.0
+  device: ARM::RteTest_ARMCM0_Dual
+  device-pack: ARM::RteTest_DFP@0.2.0
+  device-pack-path: ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.2.0
+  output:
+    - file: core0/CM0/Debug/zephyr/zephyr.elf
+      info: generate by core0.Debug+CM0
+      type: elf
+      load: symbols
+      pname: cm0_core0
+    - file: core0/CM0/Debug/zephyr/zephyr.hex
+      info: generate by core0.Debug+CM0
+      type: hex
+      load: image
+      pname: cm0_core0
+    - file: core1/CM0/Debug/zephyr/zephyr.elf
+      info: generate by core1.Debug+CM0
+      type: elf
+      load: symbols
+      pname: cm0_core1
+    - file: core1/CM0/Debug/zephyr/zephyr.hex
+      info: generate by core1.Debug+CM0
+      type: hex
+      load: image
+      pname: cm0_core1
+  system-resources:
+    memory:
+      - name: FLASH_DUAL
+        access: rx
+        start: 0x00000000
+        size: 0x00080000
+        pname: cm0_core0
+        default: true
+        from-pack: ARM::RteTest_DFP@0.2.0
+      - name: SRAM_DUAL
+        access: rwx
+        start: 0x80000000
+        size: 0x00020000
+        pname: cm0_core1
+        default: true
+        from-pack: ARM::RteTest_DFP@0.2.0
+      - name: IROM1
+        access: rx
+        start: 0x00000000
+        size: 0x00040000
+        default: true
+        from-pack: ARM::RteTest_DFP@0.2.0
+      - name: IRAM1
+        access: rwx
+        start: 0x20000000
+        size: 0x00020000
+        default: true
+        from-pack: ARM::RteTest_DFP@0.2.0
+    processors:
+      - core: Cortex-M0
+        revision: r0p0
+        pname: cm0_core0
+        endian: configurable
+        fpu: none
+        mpu: none
+        dsp: none
+        trustzone: none
+        mve: fp
+        pacbti: none
+        max-clock: 10000000
+        cdecp: 0x12
+      - core: Cortex-M0
+        revision: r0p0
+        pname: cm0_core1
+        endian: configurable
+        fpu: dp
+        mpu: none
+        dsp: present
+        trustzone: present
+        mve: int
+        pacbti: present
+        max-clock: 10000000
+        punits: 1
+        cdecp: 0x34
+  system-descriptions:
+    - file: ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.2.0/Device/ARM/SVD/ARMCM0.svd
+      type: svd
+  debugger:
+    name: CMSIS-DAP@pyOCD
+    protocol: swd
+    clock: 10000000
+    dbgconf: ../.cmsis/solution+CM0.dbgconf
+    start-pname: cm0_core0
+    gdbserver:
+      - port: 3333
+        pname: cm0_core0
+      - port: 3334
+        pname: cm0_core1
+    telnet:
+      - pname: Core0
+        mode: server
+        port: 4444
+      - pname: Core1
+        mode: console
+      - pname: Core2                # Error: invalid mode
+        mode: invalid-mode
+      - pname: No Mode              # Error: missing required mode
+    rtt:
+      - pname: Core0
+        channel:
+          - number: 0
+            mode: stdio
+          - number: 2
+            mode: server
+            port: 4444
+          - number: 3
+            mode: systemview
+            port: 4445
+          - port: 4446               # Error: missing required channel number
+            mode: systemview-server
+          - number: 4                # Error: missing required mode
+            port: 4447
+          - number: 5                # Error: invalid mode
+            mode: invalid-mode
+      - pname: Cortex-M4             # Error: missing required channel
+        control-block:
+          auto-detect: true
+          address: 0x20000000
+          size: 4096
+
+  debug-vars:
+    vars: |
+      __var DbgMCU_CR      = 0x00000007;   // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY
+      __var TraceClk_Pin   = 0x00040002;   // PE2
+      __var TraceD0_Pin    = 0x00040003;   // PE3
+      __var TraceD1_Pin    = 0x00040004;   // PE4
+  debug-sequences:
+    - name: DebugDeviceUnlock
+      blocks:
+        - execute: |
+            Sequence("CheckID");
+    - name: DebugCoreStart
+      blocks:
+        - execute: |
+            // Replication of Standard Functionality
+            Write32(0xE000EDF0, 0xA05F0001);                                        // Enable Core Debug via DHCSR
+        - info: DbgMCU registers
+          execute: |
+            // Device Specific Debug Setup
+            Write32(0x40021018, Read32(0x40021018) | 0x00400000);                   // Set RCC_APB2ENR.DBGMCUEN
+    - name: CheckID
+      blocks:
+        - execute: |
+            __var pidr1 = 0;
+            __var pidr2 = 0;
+            __var jep106id = 0;
+            __var ROMTableBase = 0;
+
+            __ap = 0;      // AHB-AP
+
+            ROMTableBase = ReadAP(0xF8) & ~0x3;
+
+            pidr1 = Read32(ROMTableBase + 0x0FE4);
+            pidr2 = Read32(ROMTableBase + 0x0FE8);
+            jep106id = ((pidr2 & 0x7) << 4 ) | ((pidr1 >> 4) & 0xF);
+        - if: jep106id != 0x20
+          execute: |
+            Query(0, "Incorrect ID! Abort connection", 1);
+            Message(2, "Incorrect ID! Abort connection.");
+        - while: (ReadDP(DP_CTRL_STAT) & 0xA0000000) != 0xA0000000
+          timeout: 1000000
+    - name: DebugPortStop
+      blocks:
+        - execute: |
+            __var connectionFlash = ( __connection & 0xF ) == 2 ;
+            __var FLASH_BASE = 0x40022000 ;
+            __var FLASH_CR = FLASH_BASE + 0x10 ;
+            __var OBL_LAUNCH_BIT = ( 1 << 13 ) ;
+            __var FLASH_CR_Value = 0 ;
+            __var DoDebugPortStop = 1 ;
+            __var DP_CTRL_STAT = 0x4 ;
+            __var DP_SELECT = 0x8 ;
+        - if: connectionFlash && DoDebugPortStop
+          execute: |
+            DoDebugPortStop = 0 ;
+            FLASH_CR_Value = Read32( FLASH_CR ) ;
+            __errorcontrol = 1 ;
+            // write OBL_LAUNCH bit (causes a reset)
+            Write32( FLASH_CR, FLASH_CR_Value | ( OBL_LAUNCH_BIT ) ) ;
+            __errorcontrol = 0 ;
+        - if: DoDebugPortStop
+          execute: |
+            // Switch to DP Register Bank 0
+            WriteDP(DP_SELECT, 0x00000000);
+            // Power Down Debug port
+            WriteDP(DP_CTRL_STAT, 0x00000000);
+  programming:
+    - algorithm: ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.2.0/Device/ARM/Flash/CortexM4Dual.FLM
+      start: 0x000A0000
+      size: 0x00020000
+      ram-start: 0x000C0000
+      ram-size: 0x00040000
+      pname: cm0_core1
+    - algorithm: ${CMSIS_PACK_ROOT}/ARM/RteTest_DFP/0.2.0/Device/ARM/Flash/FAMILY.FLM
+      start: 0x00000000
+      size: 0x00040000
+      ram-start: 0x20000000
+      ram-size: 0x00020000
+  flash-info:
+    - name: Internal Flash 16KB
+      start: 0x0000F000
+      page-size: 0x00000040
+      blocks:
+        - count: 64
+          size: 0x00000100
+          arg: 0
+      blank-val: 0x0000000000000000
+      fill-val: 0xCCCCCCCCCCCCCCCC
+      ptime: 100000
+      etime: 1000000
+      pname: cm0_core1
+    - name: Family Flash
+      start: 0x80000000
+      page-size: 0x00000100
+      blocks:
+        - count: 64
+          size: 0x00000100
+        - count: 128
+          size: 0x00000400
+  debug-topology:
+    debugports:
+      - dpid: 0
+        accessports:
+          - apid: 0
+            index: 0
+            datapatch:
+              - address: 0xE0040FCC
+                value: 0x00000011
+                info: DEVTYPE
+              - address: 0xE0040FF0
+                value: 0x0000000D
+                info: CIDR0
+              - address: 0x1000FFFF
+                value: 0x000000CC
+                info: Family level datapatch
+      - dpid: 1
+        accessports:
+          - apid: 1
+            index: 0
+    processors:
+      - pname: cm0_core0
+        apid: 0
+        reset-sequence: ResetSystem0
+      - pname: cm0_core1
+        apid: 1
+        reset-sequence: ResetSystem1

tools/projmgr/test/src/ProjMgrSchemaCheckerUnitTests.cpp

@@ -618,3 +618,30 @@ TEST_F(ProjMgrSchemaCheckerUnitTests, SchemaCheck_CbuildSet_Contexts) {
     EXPECT_TRUE(errList.end() != errItr);
   }
 }
+
+TEST_F(ProjMgrSchemaCheckerUnitTests, SchemaCheck_CbuildRun) {
+    vector<std::pair<int, int>> expectedErrPos = {
+        // line, col
+        {  109  ,  9 },
+        {  110  ,  9 },
+        {  122  , 13 },
+        {  124  , 13 },
+        {  127  , 13 },
+        {  128  , 9  }
+    };
+
+    const string& filename = testinput_folder +
+        "/TestRunDebug/invalid_telnet_rtt_schema.cbuild-run.yml";
+    EXPECT_FALSE(Validate(filename));
+
+    // Check errors
+    auto errList = GetErrors();
+    ASSERT_EQ(errList.size(), expectedErrPos.size());
+    for (auto& errPos : expectedErrPos) {
+        auto errItr = find_if(errList.begin(), errList.end(),
+            [&](const RteError& err) {
+                return err.m_line == errPos.first && err.m_col == errPos.second;
+            });
+        EXPECT_TRUE(errList.end() != errItr);
+    }
+}