feat: add ACIR to PYC-compatible Verilog backend

[HKU-LiBoyu]

Summary

This PR adds the first low-resource ACIR-to-RTL integration slice for the
Queue/PYC path. A frozen Queue ACIR module can now be lowered through the
existing canonical PYC generator and emitted as a self-contained Verilog
artifact with the required cycle-level runtime primitives embedded.

What changed

• Add tools/acir-queue-veriloggen.py as the ACIR → canonical PYC → Verilog
  bridge, including explicit operation validation, source-tree/installed
  runtime lookup, and a lowering timeout guard.
• Add parameterized PYC-compatible Verilog runtime modules for FIFO, register,
  Popcount, and round-robin arbitration under
  resources/pyc_runtime/verilog/.
• Make the Arbiter cursor wrap Yosys-synthesizable and keep FIFO parameter
  comparisons width-safe.
• Emit correctly sized pyc.extract slices for packed fields.
• Install the bridge/runtime and make acir-queue-pycgen an explicit lit-test
  dependency.
• Add Arbiter and Popcount ACIR codegen fixtures plus a bounded Verilator smoke
  test covering Arbiter N=2/N=3/N=4, Popcount, and FIFO push/pop.

Verification

• ACIR → PYC → Verilog: Arbiter and Popcount PASS.
• Verilator lint: Arbiter and Popcount PASS.
• Verilator behavioral smoke: PYC_PRIMITIVES_SMOKE PASS.
• Yosys prep; check; stat: Arbiter and Popcount PASS with 0 problems.
• Python syntax and git diff --check: PASS.
• Verification used the existing WSL acir-queue-pycgen binary and one
  Verilator build job; no full LLVM/Ninja rebuild was started.

Scope

This is a PYC-compatible bridge for the supported Queue primitive slice. It is
not a replacement for pyCircuit pycc, and it does not introduce a second
generic primitive registry or a Direct ACIR-to-Verilog compiler. Those pieces
can follow after the PYC dialect/toolchain and qualified primitive registry are
unified.