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Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

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RDSik/verilog-transceiver

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Icarus Simulation License



My Image

Usage

Dependencies

hdlmake, make, cocotb, pytest, vivado, modelsim, python, chocolatey, winget

Installation

Download python and git:

Clone repository:

git clone --recurse-submodules https://github.com/RDSik/verilog-transceiver.git
cd verilog-transceiver

Download packages:

pip install six
pip install hdlmake
pip install cocotb
pip install pytest

Download make (add to PATH system variable the Make bin folder: C:\Program Files (x86)\GnuWin32\bin):

winget install GnuWin32.make

Build project

Build trasceiver:

cd syn
py -m hdlmake
make
vivado .\transceiver.xpr

Build only vivado project:

cd syn
py -m hdlmake
make project
vivado .\transceiver.xpr

Simulation

Modelsim simulation

Using hdlmake:

cd sim/modelsim
py -m hdlmake
make

Using cocotb (with 64 bit Python use 64 bit Modelsim):

py -m venv myenv
.\myenv\Scripts\activate.ps1
cd .\sim\cocotb
py -m pytest test.py
deactivate

Icarus simulation:

make