init commit

Author: RDSik

.gitignore

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+# gitignore template for Xilinx Vivado Design Suite
+# website: https://www.xilinx.com/support/download.html
+
+# [home]
+*.jou
+*.log
+*.debug
+*.str
+*.zip
+*.tmp
+*.rst
+*.os
+*.js
+*.pb
+*.dcp
+*.hwdef
+*.vds
+*.veo
+*.wdf
+*.vdi
+*.dmp
+*.rpx
+*.rpt
+*_stub.v
+*_stub.vhdl
+*_funcsim.v
+*_funcsim.vhdl
+.project
+
+# [dir]
+*.cache
+.metadata
+*.data
+*.ipdefs
+.Xil
+*.sdk
+*.hw
+*.ip_user_files
+
+### IP synth
+*_synth_*
+
+.jobs
+
+### project synth
+*/*.runs/synth*/*.xml
+*/*.runs/synth*/*.txt
+*/*.runs/synth*/*.sh
+*/*.runs/synth*/*.tcl
+*/*.runs/synth*/*.bat
+*/*.runs/synth*/*.xdc
+!*/*.runs/synth*/*utilization*.rpt
+
+*.runs/synth*/*.xml
+*.runs/synth*/*.txt
+*.runs/synth*/*.sh
+*.runs/synth*/*.tcl
+*.runs/synth*/*.bat
+*.runs/synth*/*.xdc
+!*.runs/synth*/*utilization*.rpt
+
+### project impl
+*/*.runs/impl*/*.xml
+*/*.runs/impl*/*.html
+*/*.runs/impl*/*.txt
+*/*.runs/impl*/*.sh
+*/*.runs/impl*/*.tcl
+*/*.runs/impl*/*.bat
+!*/*.runs/impl*/*utilization*.rpt
+
+*.runs/impl*/*.xml
+*.runs/impl*/*.html
+*.runs/impl*/*.txt
+*.runs/impl*/*.sh
+*.runs/impl*/*.tcl
+*.runs/impl*/*.bat
+!*.runs/impl*/*utilization*.rpt
+
+### block design
+*/*/bd/*/hdl
+*/*/*/bd/*/hdl
+
+*/*/bd/*/*.xdc
+*/*/*/bd/*/*.xdc
+
+*/*/bd/*/ip/*/*.xdc
+*/*/*/bd/*/ip/*/*.xdc
+
+*/*/bd/*/ip/*/*/
+*/*/*/bd/*/ip/*/*/
+
+*/*/bd/*/ip/*/*.vhd
+*/*/*/bd/*/ip/*/*.vhd
+
+*/*/bd/*/ip/*/*.xml
+*/*/*/bd/*/ip/*/*.xml
+
+*.c
+*.h
+*.vho
+*.html
+*/*/bd/*/ip/*/*.tcl
+*/*/*/bd/*/ip/*/*.tcl
+hw_handoff
+ipshared

Manifest.py

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+modules = {
+    "local" : [
+        "modules",
+        "top",
+    ],
+}

README.md

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+# Usage
+
+## Dependencies 
+
+`hdlmake`, `make`, `vivado`, `python`
+
+## Clone repository:
+```bash
+git clone --recurse-submodules https://github.com/RDSik/FPGA_transceiver.git
+cd FPGA_trasceiver
+# git clone --recurse-submodules https://github.com/RDSik/FPGA_transceiver.git
+# git submodule update --init
+```
+
+## Requirements installation:
+```bash
+pip install six
+pip install hdlmake
+winget install GnuWin32.make # add to PATH system variable the Make bin folder: C:\Program Files (x86)\GnuWin32\bin
+```
+
+## Build FPGA_trasceiver:
+```bash
+cd syn
+hdlmake
+make
+```
+
+## Only create Vivado project
+```bash
+cd syn
+hdlmake
+make project
+```
+
+## FPGA_trasceiver test
+
+```bash
+cd sim
+hdlmake
+make
+vsim work.receiver_tb
+```

modules/Manifest.py

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+modules = {
+    "local" : [
+        "receiver",
+    ],
+}

modules/receiver/Manifest.py

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+files = [
+    "receiver.v",
+]

modules/receiver/receiver.v

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+`timescale 1ns / 1ns
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 18.09.2023 20:41:16
+// Design Name: 
+// Module Name: receiver
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module receiver #(
+    parameter DATA_WIDTH = 9
+) (
+    input                   clk,
+    input                   arst, // asynchronous reset
+    input                   in,
+    output                  done,
+    output [DATA_WIDTH-1:0] out
+);
+    
+    parameter [3:0] 
+                    START = 4'd0, 
+                    D0 = 4'd1, 
+                    D1 = 4'd2, 
+                    D2 = 4'd3, 
+                    D3 = 4'd4, 
+                    D4 = 4'd5, 
+                    D5 = 4'd6, 
+                    D6 = 4'd7, 
+                    D7 = 4'd8,
+                    D8 = 4'd9, 
+                    STOP = 4'd10,
+                    DONE = 4'd11;                    
+    
+    reg [3:0]            state; 
+    reg [3:0]            next_state;
+    reg [DATA_WIDTH-1:0] data;
+    
+    always @(*)
+        begin
+            case (state)
+                START: begin
+                    if (in) // 1- start bit
+                        next_state = D0;
+                    else
+                        next_state = START; 
+                end
+                D0: begin
+                    next_state = D1;
+                    data[0] = in;
+                end
+                D1: begin
+                    next_state = D2;
+                    data[1] = in;
+                end
+                D2: begin
+                    next_state = D3;
+                    data[2] = in;
+                end
+                D3: begin
+                    next_state = D4;
+                    data[3] = in;
+                end
+                D4: begin
+                    next_state = D5;
+                    data[4] = in;
+                end
+                D5: begin
+                    next_state = D6;
+                    data[5] = in;
+                end
+                D6: begin
+                    next_state = D7;
+                    data[6] = in;
+                end
+                D7: begin
+                    next_state = D8;
+                    data[7] = in;
+                end
+                D8: begin
+                    next_state = STOP;                    
+                    data[8] = (data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7])^in; // parity bit
+                end
+                STOP: begin
+                    if (in && data[8]) // 1 - stop bit
+                        next_state = DONE;                        
+                    else 
+                        next_state = START;
+                end
+                DONE: begin                    
+                    if (!in)
+                        next_state = START;
+                    else
+                        next_state = D0;
+                end                         
+                default: next_state = START;
+            endcase 
+        end
+        
+    always @(posedge clk or posedge arst)
+        begin
+            if (arst)
+                state <= START;
+            else
+                state <= next_state;
+        end
+        
+    assign done = (state == DONE);
+    assign out = done ? data : 9'd0;
+    
+endmodule

sim/Manifest.py

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+action = "simulation"
+sim_tool = "modelsim"
+sim_top = "receiver_tb"
+
+modules = {
+    "local" : [
+        "../tb", 
+        "../",
+    ],
+}

syn/Manifest.py

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+target = "xilinx"
+
+action = "synthesis"
+
+syn_device = "xc7z020clg484-1"
+syn_package = ""
+syn_grade = "-3"
+syn_top = "receiver_top"
+syn_project = "receiver"
+syn_tool = "vivado"
+
+files = [
+    'receiver.xdc'
+]
+
+modules = {
+    "local" : [
+        "../",
+    ],
+}

syn/receiver.xdc

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+`timescale 1ns / 1ns
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 18.09.2023 21:45:38
+// Design Name: 
+// Module Name: receiver_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module receiver_tb();
+
+reg        clk;
+reg        arst;
+reg        in;
+
+wire       done;
+wire [8:0] out;
+wire [3:0] state;
+wire       parity;
+
+integer i;
+
+receiver #(
+    .DATA_WIDTH (9)
+) dut (
+    .clk  (clk),
+    .arst (arst),
+    .in   (in),
+    .done (done),
+    .out  (out)
+);
+
+assign state = dut.state;
+assign parity = dut.data[8];
+
+initial 
+    begin        
+        clk = 0; 
+        #5; arst = 1;
+        #5; arst = 0;
+        for (i = 0; i <= 127; i = i + 1)
+            begin
+                #5; in = $urandom_range(0,1); 
+            end 
+    end
+
+always #5 clk = !clk;
+
+initial 
+    $monitor("time=%g, clk=%b - in=%b - done=%b - out=%b", $time, clk, in, done, out);
+	
+initial 
+	#550 $stop;
+
+endmodule

tb/receiver_tb.v

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+files = [
+    "receiver_top.v",
+]