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author
Dmitry Ryabikov
committed
Simulation in vivado with hdlmake working
1 parent 709995b commit e1aec97

22 files changed

+565
-24
lines changed

‎.gitignore

+6-2
Original file line numberDiff line numberDiff line change
@@ -2,10 +2,14 @@ syn/*
22
!Manifest.py
33
!add_files.tcl
44
!transceiver.xdc
5-
top/sim/*
5+
top/sim/modelsim/*
6+
!Manifest.py
7+
!sin_value.dat
8+
!neg_sin_value.dat
9+
!vsim.do
10+
top/sim/vivado/*
611
!Manifest.py
712
!sin_value.dat
813
!neg_sin_value.dat
9-
!sin_value.m
1014
platform/xilinx/clk_wiz/*
1115
!clk_wiz.xci

‎modules/bpsk/bpsk_demodulator.v

-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
`timescale 1ps / 1ps
2-
31
module bpsk_demodulator #(
42
parameter SAMPLE_NUMBER = 256,
53
parameter SAMPLE_WIDTH = 12,

‎modules/bpsk/bpsk_modulator.v

-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
`timescale 1ps / 1ps
2-
31
module bpsk_modulator #(
42
parameter SAMPLE_NUMBER = 256,
53
parameter SAMPLE_WIDTH = 12,

‎modules/bpsk/bpsk_top.v

-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
`default_nettype none
2-
`timescale 1ps / 1ps
32

43
module bpsk_top #(
54
parameter SAMPLE_NUMBER = 256,

‎modules/bpsk/sin_generator.v

-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
`timescale 1ps / 1ps
2-
31
module sin_generator #(
42
parameter SAMPLE_NUMBER = 256,
53
parameter SAMPLE_WIDTH = 12

‎modules/hamming/hamming_decoder.v

-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
`timescale 1ps / 1ps
2-
31
module hamming_decoder (
42
input wire clk,
53
input wire rst_n,

‎modules/hamming/hamming_encoder.v

-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
`timescale 1ps / 1ps
2-
31
module hamming_encoder (
42
input wire clk,
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input wire rst_n,

‎modules/hamming/humming_coder12_8.v

-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
11
`default_nettype none
2-
`timescale 1ps / 1ps
32

43
module humming_coder12_8 (
54
input wire clk,

‎platform/xilinx/clk_wiz/clk_wiz.xci

+7
Original file line numberDiff line numberDiff line change
@@ -685,17 +685,24 @@
685685
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
686686
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
687687
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/>
688+
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
689+
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
690+
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
691+
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
688692
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
689693
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
690694
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/>
691695
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/>
692696
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/>
693697
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT1_PORT" xilinx:valueSource="user"/>
698+
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT2_PORT" xilinx:valueSource="user"/>
694699
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
695700
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
696701
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
702+
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
697703
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
698704
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
705+
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
699706
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMARY_PORT" xilinx:valueSource="user"/>
700707
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMITIVE" xilinx:valueSource="user"/>
701708
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_LOCKED" xilinx:valueSource="user"/>

‎syn/add_files.tcl

+2-2
Original file line numberDiff line numberDiff line change
@@ -3,9 +3,9 @@ open_project transceiver.xpr
33
read_ip ../platform/xilinx/clk_wiz/clk_wiz.xci
44
generate_target all [get_files *clk_wiz.xci]
55

6-
read_mem ../top/sim/sin_value.dat
6+
read_mem ../top/sim/modelsim/sin_value.dat
77

8-
read_mem ../top/sim/neg_sin_value.dat
8+
read_mem ../top/sim/modelsim/neg_sin_value.dat
99

1010
close_project
1111
exit

‎top/sim/iverilog/Manifest.py

+11
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@@ -0,0 +1,11 @@
1+
action = "simulation"
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sim_tool = "iverilog"
3+
sim_top = "transceiver_tb"
4+
5+
sim_post_cmd = "vvp tranceiver_tb.vvp; gtkwave out.vcd"
6+
7+
modules = {
8+
"local" : [
9+
"../../tb/",
10+
],
11+
}

‎top/sim/Manifest.py renamed to ‎top/sim/modelsim/Manifest.py

+1-1
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@@ -6,6 +6,6 @@
66

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modules = {
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"local" : [
9-
"../tb/",
9+
"../../tb/",
1010
],
1111
}

‎top/sim/neg_sin_value.dat renamed to ‎top/sim/modelsim/neg_sin_value.dat

File renamed without changes.

‎top/sim/sin_value.dat renamed to ‎top/sim/modelsim/sin_value.dat

File renamed without changes.

‎top/sim/modelsim/vsim.do

+5
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@@ -0,0 +1,5 @@
1+
vcd file transceiver_tb.vcd;
2+
vcd add -r /*;
3+
add wave *
4+
run 25000ps;
5+
view wave;

‎top/sim/vivado/Manifest.py

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@@ -0,0 +1,11 @@
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action = "simulation"
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sim_tool = "vivado_sim"
3+
sim_top = "transceiver_tb"
4+
5+
sim_post_cmd = "xsim %s -gui" % sim_top
6+
7+
modules = {
8+
"local" : [
9+
"../../tb/",
10+
],
11+
}

‎top/sim/vivado/neg_sin_value.dat

+256
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@@ -0,0 +1,256 @@
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100000000000
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011111001110
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011110011100
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011101101001
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011100110111
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011100000101
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011011010100
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011010100010
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011001110001
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011000111111
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011000001110
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010111011110
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010110101110
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010101111110
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010101001110
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010100011111
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010011110000
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010011000010
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010010010101
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010001100111
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010000111011
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010000001111
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001111100011
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001110111001
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001110001110
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001101100101
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001100111100
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001100010100
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001011101101
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001011000111
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001010100001
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001001111100
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001001011000
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000111110010
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000111010001
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000110010011
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000101110110
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000101011010
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000100111110
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000100100100
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000011110010
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000011011011
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000011000101
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000010110000
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000001111000
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000001101000
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000001011001
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000001001011
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000000111110
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000000110010
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000000101000
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000000011111
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000000010111
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000000010000
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000000001010
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000000000110
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000000000011
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000000000001
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000000000000
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000000000001
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000000000011
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000000000110
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000000001010
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000000010000
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000000010111
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000000011111
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000000101000
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000000110010
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000000111110
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000001001011
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000001011001
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000001101000
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000001111000
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000010110000
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000011110010
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111101010000
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111101100100
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111101110110
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111110001000
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111110011000
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111110100111
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111110110101
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111111000010
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111111001110
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111111011000
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111111100001
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111111101001
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111111110000
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111111110110
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111111111010
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111111111101
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111111111111
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111111111111
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111111111111
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111111111101
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111111111010
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111111110110
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111111110000
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111111101001
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111111100001
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111111011000
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101000100010
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100111110010
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100111000001
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100101011110
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100100101100
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100011111011
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100011001001
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100010010111
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100001100100
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100000110010

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