merge main into amd-staging#3320
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rocm-cciapp[bot] merged 122 commits intoJul 11, 2026
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Simplify the toolchain implementations by collapsing them into one. Previously we had a confusing split. The AMDGPUToolChain base class implemented much of the base support. It was subclassed by ROCMToolChain, which would have been more accurately described as the offloading subclass. That was further subclassed into HIP and OpenMP specific subclasses. Deleting those two is the important part of this change. There was code duplication, and features arbitrarily handled in one but not the other. The offload kind is passed in almost everywhere if you really need to know the original language. However, I consider this an antifeature, and it is really poor QoI to have the HIP and OpenMP toolchains behave differently in any way. The platform should be consistent and the driver behaviors should not depend on the language. There is additional mess in the handling of spirv, which this only partially addresses. There are two different spirv toolchain paths, which for some reason is keyed off of the amdhsa OS, which is not the property that should change this. I think it will ultimately be simplier to just merge all spirv handling into HIPSPV. The copy-paste machine did most of the work here, and I manually applied some logical fixups that became apparent after the merge. Co-Authored-By: Claude <noreply@anthropic.com>
IRtranslator now translates bfloat. Switch tablegen to use extendedLLTs. Around 300 regression tests fail to inst-select because GIM_SwitchType does not accept LLT::scalar. Around 100 mir inst select tests had input updated to i32/f32 and select successfully. Then there are 24 various crashes, mostly combiner or machine-verifier, those tests are disabled. Most problems come from mixing s32 with i32/f32 and the way operator== works with extendedLLTs compared to GIM_SwitchType. In general, for inst-select fixes, I think it would be best to avoid explicit use of LLT::scalar in lowering to avoid mixing it with LLT::integer/LLT::float See inst-select-extendedLLTs.mir and inst-select-extendedLLTs-err.mir.
`performShlCombine` introduced a `v2i32 truncate x:v2i64`. This pattern is not legal, and is normally expanded by the legalizer. However, since the combine is done after legalization the illegal pattern remains. This happens on `gfx1251` since it has legal `shl v2i64` instructions (due to `PackedU64Ops`). This patch introduces a legal pattern for `v2i32 truncate x:v2i64`.
Avoids verifier failure regressions in a future change.
[Clang][Driver] Parallelize device cc1 jobs for offload arches Large offload builds can target many device architectures. A common ROCm build can target around ten `--offload-arch=` values. For a large single translation unit, the offload device cc1 work before clang-linker-wrapper can become a build-time bottleneck. Those per-architecture jobs are independent, but the driver ran them serially, so `--offload-jobs=` only helped the later wrapper work. Borrow the parallel job mechanism used by clang-linker-wrapper for the pre-wrapper device cc1 jobs. Device job construction marks eligible compile and backend jobs with an offload parallel group. The generic executor only consumes that opt-in metadata for adjacent device jobs with distinct bound architectures. The parallel path is disabled for driver-side output modes and callbacks so existing serial output handling is preserved. This is NFC for non-offload compilation.
Stop using LLT::scalar for argument lowering in AMDGPUCallLowering. Mostly straightforward, worth noting that some places now require a bitcast between integer and float.
…sions (llvm#208439) Allocators are only required to be explicitly convertible between different types. `shared_ptr` currently requires implicit conversions, however. This is a regression introduced by llvm#200401.
…preferred (llvm#202909) Extends the AArch64 specific DAG combine for get_active_lane_mask to split up a single wide active lane mask used by a series of subvector extracts into several smaller get_active_lane_mask nodes if preferred. This PR is part of a series of changes leading to the use of wide active lane masks as the canonical form in LoopVectorize when choosing to interleave and tail-fold loops. llvm#193757 is the original PR where this was discussed. The motivation for this PR is to leave the decision on which form of the IR to use up to the target. This will remove the need for more complex decisions and transformations during vectorisation to query whether it's best to create a single mask + extracts or multiple smaller masks.
…#207045) This continues expanding our set of benchmarks. Assisted by Claude
When dollars are supported in identifiers, we should be consistent. Fixes llvm#173985 Fixes llvm#171190
We already use the C++11 spelling for libc++, and there isn't much of a reason not to use it. Except for the changes in `cxxabi.h` this is even fully standard code.
The following preprocessing directive is not a C++ module directive, don't handle it in C++ module subroutine. ```cpp #module ``` Fixes llvm#179220. Signed-off-by: yronglin <yronglin777@gmail.com>
When converting `select cond, (load p1), (load p2)` to `load (select cond, p1, p2)`, if `cond` is poison, originally this would result in a `poison` result, while after the transform it would result in a load of poison, which is immediate UB. Fix this by freezing the condition. Fixes llvm#208611.
…lvm#208269) Stop using LLT::scalar in custom lowering in AMDGPULegalizerInfo. The exception is S1 since it seems to work fine. Does not change legalizer actions. In general this is intended as a mechanical step in amdgpu's switch to extended LLTs, just try to avoid LLT::scalar in instructions generated after IRtranslator, since it seems like a step in the right direction. Some tests remove -global-isel-abort=2 since GIM_SwitchType no longer fails on LLT::scalar. Exposes a couple of new failures with 16bit bitcast.
… rounding (llvm#207373) The overflow path in `__hexagon_fmadf5` computed the round-mode predicate (inf vs. largest-finite) into p0, but then overwrote p0 with `dfcmp.eq(ATMP,ATMP)` before consuming it. Since ATMP is +inf, `dfcmp.eq(ATMP,ATMP)` is always true, so CTMP was unconditionally set to infinity and the rounding-mode decision was discarded. As a result, a finite-magnitude overflow returned +/-inf in every rounding mode. Fix: Fuse the selection into a single packet so the round-mode predicate selects inf-vs-DBL_MAX, and recompute p0 = dfcmp.eq afterwards only to raise the exception flags which matching the correct sequence already used by dfdiv.S. Also, I've added a regression test (`hexagon_fmadf5_test.c`) covering FMA special cases: NaN propagation, invalid operations (0*inf, inf+(-inf)), infinity propagation, exact results, signed-zero of exact sums, the single- rounding property, overflow under all rounding modes, and subnormal results. Please let me know if this test for the builtin is in the right place, or if it should be in some place else. Assisted by: GPT 5.5 Signed-off-by: Zain Siddavatam <zsiddava@qti.qualcomm.com>
…lvm#208726) Bug fix. In the transfer function (one of the cast cases), the loop adding synthetic fields to the derived record storage location was incorrectly nested inside the loop that iterates over modeled fields (`getModeledFields`). If the derived class has 0 modeled fields, `getModeledFields(Derived)` is empty. Consequently, synthetic fields were never added to the storage location, causing an assertion failure in `StorageLocation::getSyntheticField` when initializing field values. This patch moves the synthetic fields loop outside of the modeled fields loop and adds a regression unit test in `TransferTest.cpp`.
…ved supers (llvm#208521) `determineCalleeSaves()` in `AArch64FrameLowering` double counts the D8-D15/Q8-Q1 overlap - fixed by skipping sub-registers whose super is saved. Fixes llvm#204564
No one outside Apple can access the associated radars and understand what these tests are about. These tests have other problems, but this makes them at least possible to comprehend for everyone.
Replace most of the test's setup code with modern test utils and expand the test case to cover more common or potentially problematic uses of unions.
This is a new modern test for long types that replaces the test logic from `API/types` test that is about to be deleted. This is a distinct test from the normal integer types due to long depending on data models which change depending on platform. See also llvm#208402 assisted-by: claude
This is a new modern test for recursive types that self-reference themselves via function pointers. This replaces the test logic from `API/types` test that is about to be deleted. See also llvm#208402 assisted-by: claude
This is a new modern test for char types that replaces the test logic from `API/types` test that is about to be deleted. See also llvm#208402 assisted-by: claude
This moves some of the tested logic from the `types/` test that is about to be deleted to the already existing c/blocks test. See also llvm#208402 assisted-by: claude
…ndexes (llvm#207202) The main use case is to serve windows index on linux server. Without this change server wasn't able to check if project_root path is absolute and was closed with error: "Index root should be an absolute path." This change is meant to solve issue: clangd/clangd#2646
…e and gather/scatter ops (llvm#205869) Extend negative stride checks to MaskedLoadOp, MaskedStoreOp, GatherOp, and ScatterOp to match LoadOp and StoreOp behavior. Depends on: llvm#204611. AI Disclaimer: I used AI for the tests. @banach-space @dcaballe If you look at the latest commit, you can see why the integration tests were failing in llvm#204842. Those two calls were added in this PR, I sincerely apologize to you! --------- Signed-off-by: Federico Bruzzone <federico.bruzzone.i@gmail.com>
…lvm#207299) The loop tracing a mask back to its creation op assumed the chain always ends at a create_mask/constant_mask/arith.constant, a block-argument mask made it fall through to isa<> on a null op (segfault), and any other unhandled defining op spun it forever. Fixes llvm#206928 Claude Fable 5 did assist with this.
…lvm#199371) The existing path emits N x vpinsrb for buildvecs whose elements are loads at a regular byte stride larger than the element size: ```asm movzbl 216(%rsp), %eax vmovd %eax, %xmm0 vpinsrb $1, 224(%rsp), %xmm0, %xmm0 vpinsrb $2, 232(%rsp), %xmm0, %xmm0 ... vpinsrb $15, 336(%rsp), %xmm0, %xmm0 ``` This patch adds a strided-load path to EltsFromConsecutiveLoads that folds these into wide load(s) + vector truncation: ```asm vmovdqu64 216(%rsp), %zmm0 vmovdqu64 280(%rsp), %zmm1 vpmovqb %zmm0, %xmm0 vpmovqb %zmm1, %xmm1 vpunpcklqdq %xmm1, %xmm0, %xmm0 ``` The combine detects element loads at a uniform power of 2 byte stride larger than the element size, picks a wide-load size (ZMM/YMM/XMM) from the buildvec lane count, and emits X86ISD::VTRUNC for partial pieces or ISD::TRUNCATE for full pieces. Multi-piece results recombine with pairwise shuffle (partial) or CONCAT_VECTORS (full). This simplifies 12 existing X86 codegen tests where many-arg functions hit the strided pattern naturally. Also created a new test file with 14 tests covering: - 3 cases with 4-byte stride: v16i8, v8i16, and v32i8 destinations (single-piece full and 2-piece full with CONCAT_VECTORS) - 3 cases with 8-byte stride and partial truncation: v16i8 (2-piece pairwise), v16i16 (2-piece pairwise), v32i8 (4-piece pairwise tree) - 1 sub-xmm destination (v8i8) that widens to v16i8 - 3 partial-fill destinations of v32i8: trailing zero padding, INSERT_SUBVECTOR placement at lane 16, vector shuffle placement at lane 8 - 1 reverse-stride case - 3 negative tests: volatile loads, non-uniform stride, sparse loaded positions with interleaved undefs Fixes llvm#198175
Add VPWidenPHIRecipe to the set of recipes CSE can handle. Besides their operands (incoming values), they also depend on their predecessors, so canHandle checks for that. PR: llvm#207573
This was fixed a long time ago when relanding arena support. This FIXME was missed when we folded in the deep copying to the reland. It can safely be removed, as the situation it warns about cannot happen anymore.
We don't support building LLVM without python in any configuration; clarify that it's a hard requirement.
These do not follow the style guide, and Utils.h has the wrong macro definition.
This implements C++26's expansion statements, i.e. [P1306R5](https://wg21.link/P1306R5). An expansion statement is implemented using a number of new AST nodes. Since an expansion statement is a template, we need it to be a dependent DeclContext, but only nodes that inherit from Decl can be DeclContexts, for which reason this introduces a CXXExpansionStmtDecl. This holds a synthesised constant template parameter used as the expansion index as well as a 'CXXExpansionStmtPattern' and a 'CXXExpansionStmtInstantiation. These two AST nodes are similar to the semantic vs syntactic form of an InitListExpr: the 'Pattern' represents an unexpanded expansion statement, and the resulting AST after expansion is stored in an 'Instantiation'. Since expansion statements require us to perform template instantiation *inside* a function without instantiating the rest of a function, I had to remove a number of assertions in the template instantiation engine (e.g. the assertion that a function parameter must always have an instantiation by the time we encounter a DeclRefExpr to it no longer holds). For more implementation details, see the corresponding doc comments in DeclTemplate.h and StmtCXX.h. There is some follow up work to be done after this lands, which is tracked in llvm#207776.
…#208838) llvm#188049 changed the formatting of `register read` output. A few tests are failing now due to small space changes.
llvm#208812) Continue migrating command-line target spelling on RUN lines to the folded amdgpu subarch triple form, covering the remaining Transforms tests in this group. Co-Authored-By: Claude <noreply@anthropic.com> (Claude-Opus-4.8)
…ts (llvm#201679) NVPTX does not support direct PTX conversion instructions between floating point types and integer types wider than 64 bits. Previously, such conversions could reach instruction selection and fail with an _unsupported library call operation_ error. Reproducer on godbolt: https://godbolt.org/z/G6Yr9cE1d This patch sets the maximum supported fp/int conversion width to 64 bits so larger conversions are expanded before instruction selection. It also adds a regression test for 128-bit integer/floating-point conversions. Related to llvm#191013 Co-authored-by: Justin Fargnoli <jfargnoli@nvidia.com>
…n ForEachMappedRegion (llvm#208358) Likely related to llvm#84482 and llvm#21068 Assisted-by: Gemini
…static variables in lexical block scopes (6/7) (llvm#187927)" SPIR-V changes needed This reverts commit d58b056.
ronlieb
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dpalermo
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Jul 11, 2026
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