Add IOMMU driver, hpm iommu patch and irqbypass patch.#123
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mainline inclusion commit 5aa3c0cf5bba6437c9e63a56f684f61de8b503d6 category: bugfix bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Users of the IRQCHIP_PLATFORM_DRIVER_{BEGIN,END} helpers rely on a fwspec containing only the fwnode (and crucially a number of parameters set to 0) together with a DOMAIN_BUS_ANY token to check whether a parent irqchip has probed and registered a domain. Since de1ff306dcf4 ("genirq/irqdomain: Remove the param count restriction from select()"), ops->select() is called unconditionally, meaning that irqchips implementing select() now need to handle ANY as a match. Instead of adding more esoteric checks to the individual drivers, add that condition to irq_find_matching_fwspec(), and let it handle the corner case, as per the comment in the function. This restores the functionality of the above helpers. Fixes: de1ff306dcf4 ("genirq/irqdomain: Remove the param count restriction from select()") Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reported-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20240220114731.1898534-1-maz@kernel.org Link: https://lore.kernel.org/r/20240219-gic-fix-child-domain-v1-1-09f8fd2d9a8f@linaro.org Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 3095cc0d5b2c246ddfcb18f54ed5557640224b6a category: cleanup bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- In preparation for providing a special allocation function for wired interrupts which are connected to a wire to MSI bridge, split the inner workings of msi_domain_alloc_irq_at() out into a helper function so the code can be shared. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240127161753.114685-9-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 2d566a498d6483ba986dadc496f64a20b032608f category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Provide a domain bus token for the upcoming support for wire to MSI device domains so the domain can be distinguished from regular device MSI domains. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240127161753.114685-10-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 9d1c58c8004653b37721dd7b16f4360216778c94 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- To support wire to MSI domains via the MSI infrastructure it is required to use the firmware node of the device which implements this for creating the MSI domain. Otherwise the existing firmware match mechanisms to find the correct irqdomain for a wired interrupt which is connected to a wire to MSI bridge would fail. This cannot be used for the general case because not all devices provide firmware nodes and all regular per device MSI domains are directly associated to the device and have not be searched for. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240127161753.114685-11-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 0ee1578b00bcf5ef8e7955f0c6f02a624443eb29 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- To support wire to MSI bridges proper in the MSI core infrastructure it is required to have separate allocation/free interfaces which can be invoked from the regular irqdomain allocaton/free functions. The mechanism for allocation is: - Allocate the next free MSI descriptor index in the domain - Store the hardware interrupt number and the trigger type which was extracted by the irqdomain core from the firmware spec in the MSI descriptor device cookie so it can be retrieved by the underlying interrupt domain and interrupt chip - Use the regular MSI allocation mechanism for the newly allocated index which returns a fully initialized Linux interrupt on succes This works because: - the domains have a fixed size - each hardware interrupt is only allocated once - the underlying domain does not care about the MSI index it only cares about the hardware interrupt number and the trigger type The free function looks up the MSI index in the MSI descriptor of the provided Linux interrupt number and uses the regular index based free functions of the MSI core. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240127161753.114685-12-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit e49312fe09df36cc4eae0cd6e1b08b563a91e1bc category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Reroute interrupt allocation in irq_create_fwspec_mapping() if the domain is a MSI device domain. This is required to convert the support for wire to MSI bridges to per device MSI domains. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240127161753.114685-13-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 9bbe13a5d414a7f8208dba64b54d2b6e4f7086bd category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Some platform-MSI implementations require that power management is redirected to the underlying interrupt chip device. To make this work with per device MSI domains provide a new feature flag and let the core code handle the setup of dev->pm_dev when set during device MSI domain creation. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240127161753.114685-14-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 9dbaf381008dfa2fad6225633004f7adb1bac252 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Extend the ISA string parsing to detect the Smstateen extension. If the extension is enabled then access to certain 'state' such as AIA CSRs in VS mode is controlled by *stateen0 registers. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit a4f5f39849f39f62f5d4e88cbb600f95f927003d category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Add an entry for the Smstateen extension to the riscv,isa-extensions property. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 55d2a0bd5eadaade850efa9d3a7ffbb0aeb67198 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Recently, we found that cross-die access to pagetable pages on ARM64 machines can cause performance fluctuations in our business. Currently, there are no PMU events available to track this situation on our ARM64 machines, so accurate pagetable accounting can help to analyze this issue, but now the PUD level pagetable accounting is missed. So introduce pagetable_pud_ctor/dtor() to help to get accurate PUD pagetable accounting, as well as converting the architectures which use generic PUD pagetable allocation to add corresponding PUD pagetable accounting. Moreover this patch will mark the PUD level pagetable with PG_table flag, which will help to do sanity validation in unpoison_memory(). On my testing machine, I can see more pagetables statistics after the patch with page-types tool: Before patch: flags page-count MB symbolic-flags long-symbolic-flags 0x0000000004000000 27326 106 __________________________g_________________ pgtable After patch: 0x0000000004000000 27541 107 __________________________g_________________ pgtable Link: https://lkml.kernel.org/r/876c71c03a7e69c17722a690e3225a4f7b172fb2.1695017383.git.baolin.wang@linux.alibaba.com Signed-off-by: Baolin Wang <baolin.wang@linux.alibaba.com> Acked-by: Mike Rapoport (IBM) <rppt@kernel.org> Acked-by: Vishal Moola (Oracle) <vishal.moola@gmail.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Borislav Petkov <bp@alien8.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Matthew Wilcox (Oracle) <willy@infradead.org> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 8246601a7d391ce8207408149d65732f28af81a1 category: bugfix bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 If non-leaf PTEs I.E pmd, pud or p4d is modified, a sfence.vma is a must for safe, imagine if an implementation caches the non-leaf translation in TLB, although I didn't meet this HW so far, but it's possible in theory. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Fixes: c5e9b2c2ae82 ("riscv: Improve tlb_flush()") Link: https://lore.kernel.org/r/20231219175046.2496-2-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 40d1bb92a49313b3e0dc5513fdd2578362c40312 category: cleanup bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- This is to prepare for enabling MMU_GATHER_RCU_TABLE_FREE. No functionality changes. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20231219175046.2496-3-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 69be3fb111e73bd025ce6d2322371da5aa497c70 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- In order to implement fast gup we need to ensure that the page table walker is protected from page table pages being freed from under it. riscv situation is more complicated than other architectures: some riscv platforms may use IPI to perform TLB shootdown, for example, those platforms which support AIA, usually the riscv_ipi_for_rfence is true on these platforms; some riscv platforms may rely on the SBI to perform TLB shootdown, usually the riscv_ipi_for_rfence is false on these platforms. To keep software pagetable walkers safe in this case we switch to RCU based table free (MMU_GATHER_RCU_TABLE_FREE). See the comment below 'ifdef CONFIG_MMU_GATHER_RCU_TABLE_FREE' in include/asm-generic/tlb.h for more details. This patch enables MMU_GATHER_RCU_TABLE_FREE, then use *tlb_remove_page_ptdesc() for those platforms which use IPI to perform TLB shootdown; *tlb_remove_ptdesc() for those platforms which use SBI to perform TLB shootdown; Both case mean that disabling interrupts will block the free and protect the fast gup page walker. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20231219175046.2496-4-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 3f910b7a522e064d7261f31a00d9c9dca31d902a category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Activate the fast gup for riscv mmu platforms. Here are some GUP_FAST_BENCHMARK performance numbers: Before the patch: GUP_FAST_BENCHMARK: Time: get:53203 put:5085 us After the patch: GUP_FAST_BENCHMARK: Time: get:17711 put:5060 us The get time is reduced by 66.7%! IOW, 3x get speed! Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Link: https://lore.kernel.org/r/20231219175046.2496-5-jszhang@kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 3c46fc5b5507be1f4aa144a1fbd83b0ccba04cc6 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- The RISC-V advanced interrupt architecture (AIA) extends the per-HART local interrupts in following ways: 1. Minimum 64 local interrupts for both RV32 and RV64 2. Ability to process multiple pending local interrupts in same interrupt handler 3. Priority configuration for each local interrupts 4. Special CSRs to configure/access the per-HART MSI controller Add support for #1 and RVCK-Project#2 described above in the RISC-V intc driver. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240222094006.1030709-9-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 678c607ecf8a9b1b2ea09c367877164ba66cb11f category: bugfix bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Use riscv_intc_aia_irq() as the low-level interrupt handler instead of the existing riscv_intc_irq() default handler to make demultiplexing work correctly. Also print "using AIA" in the INTC boot banner when AIA is available. Fixes: 3c46fc5b5507 ("irqchip/riscv-intc: Add support for RISC-V AIA") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240226040746.1396416-2-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit ca5b0b717b75d0f86f7f5dfe18369781bec742ad category: bugfix bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- riscv_intc_custom_base is initialized to BITS_PER_LONG, so the second check passes even though AIA provides 64 interrupts. Adjust the condition to only check the custom range for interrupts outside the standard range, and adjust the standard range when AIA is available. Fixes: 3c46fc5b5507 ("irqchip/riscv-intc: Add support for RISC-V AIA") Fixes: 678c607ecf8a ("irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20240312212813.2323841-1-samuel.holland@sifive.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 5b98d210ac1e4eb35abfbd940df50dec10ae81e1 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- A future user of the matrix allocator, does not know the size of the matrix bitmaps at compile time. To avoid wasting memory on unnecessary large bitmaps, size the bitmap at matrix allocation time. Signed-off-by: Björn Töpel <bjorn@rivosinc.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240222094006.1030709-11-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 0151a8db49b0a88f967dca0ea5ae2bee2d67b22a category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Add DT bindings document for the RISC-V incoming MSI controller (IMSIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Björn Töpel <bjorn@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240307140307.646078-2-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 21a8f8a0eb35ceb21e2c9ddd87468bc3b5ac87c0 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- The RISC-V advanced interrupt architecture (AIA) specification defines a new MSI controller called incoming message signalled interrupt controller (IMSIC) which manages MSI on per-HART (or per-CPU) basis. It also supports IPIs as software injected MSIs. (For more details refer https://github.com/riscv/riscv-aia) Add an early irqchip driver for RISC-V IMSIC which sets up the IMSIC state and provide IPIs. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Björn Töpel <bjorn@rivosinc.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Link: https://lore.kernel.org/r/20240307140307.646078-3-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 027e125acdbad79e9a7274940e8bf92299b208af category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- The Linux platform MSI support allows per-device MSI domains so add a platform irqchip driver for RISC-V IMSIC which provides a base IRQ domain with MSI parent support for platform device domains. The IMSIC platform driver assumes that the IMSIC state is already initialized by the IMSIC early driver. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Björn Töpel <bjorn@rivosinc.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Link: https://lore.kernel.org/r/20240307140307.646078-4-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 35d77eb7b974f62aaef5a0dc72d93ddb1ada4074 category: bugfix bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Currently, the following warning is observed on the QEMU virt machine: genirq: irq_chip APLIC-MSI-d000000.aplic did not update eff. affinity mask of irq 12 The above warning is because the IMSIC driver does not set the initial value of effective affinity in the interrupt descriptor. To address this, initialize the effective affinity in imsic_irq_domain_alloc(). Fixes: 027e125acdba ("irqchip/riscv-imsic: Add device MSI domain support for platform devices") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240413065210.315896-1-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 4a1361e9a5c5dbb5c9f647762ae0cb1a605101fa category: bugfix bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- The "per-CPU IDs ... at base ..." info log is outputting a physical address, not a PPN. Fixes: 027e125acdba ("irqchip/riscv-imsic: Add device MSI domain support for platform devices") Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/all/20240909085610.46625-2-ajones@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 5c5a71d0434093cd42d09afd4e2032c0b16a7da8 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- The Linux PCI framework supports per-device MSI domains for PCI devices so extend the IMSIC driver to allow PCI per-device MSI domains. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Björn Töpel <bjorn@rivosinc.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Link: https://lore.kernel.org/r/20240307140307.646078-5-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 3b806a5a1a39d593d6fe0def2ef474402f551f91 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Add DT bindings document for RISC-V advanced platform level interrupt controller (APLIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Björn Töpel <bjorn@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Link: https://lore.kernel.org/r/20240307140307.646078-6-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 2333df5ae51ead2188d07c99e841e159a664741e category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- The RISC-V advanced interrupt architecture (AIA) specification defines advanced platform-level interrupt controller (APLIC) which has two modes of operation: 1) Direct mode and 2) MSI mode. (For more details, refer https://github.com/riscv/riscv-aia) In APLIC direct-mode, wired interrupts are forwared to CPUs (or HARTs) as a local external interrupt. Add a platform irqchip driver for the RISC-V APLIC direct-mode to support RISC-V platforms having only wired interrupts. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Björn Töpel <bjorn@rivosinc.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Link: https://lore.kernel.org/r/20240307140307.646078-7-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit efe81b7bdf7d882d0ce3d183f1571321046da8f1 category: bugfix bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- The devm_platform_ioremap_resource() function doesn't return NULL, it returns error pointers. Fix the error handling to match. Fixes: 2333df5ae51e ("irqchip: Add RISC-V advanced PLIC driver for direct-mode") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Anup Patel <anup@brainfault.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/a5a628d6-81d8-4933-81a8-64aad4743ec4@stanley.mountain Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit ca8df97fe6798afbe395fc4a8e23bac0c7fbd248 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- The RISC-V advanced platform-level interrupt controller (APLIC) has two modes of operation: 1) Direct mode and 2) MSI mode. (For more details, refer https://github.com/riscv/riscv-aia) In APLIC MSI-mode, wired interrupts are forwared as message signaled interrupts (MSIs) to CPUs via IMSIC. Extend the existing APLIC irqchip driver to support MSI-mode for RISC-V platforms having both wired interrupts and MSIs. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Björn Töpel <bjorn@rivosinc.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Link: https://lore.kernel.org/r/20240307140307.646078-8-apatel@ventanamicro.com Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit cdc66553c4130735f0a2db943a5259e54ff1597a category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- Introduce cpumask_first_and_and() to get intersection between 3 cpumasks, free of any intermediate cpumask variable. Instead, cpumask_first_and_and() works in-place with all inputs and produces desired output directly. Signed-off-by: Dawei Li <dawei.li@shingroup.cn> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Yury Norov <yury.norov@gmail.com> Link: https://lore.kernel.org/r/20240416085454.3547175-2-dawei.li@shingroup.cn Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
mainline inclusion commit 5d650d1eba876717888a0951ed873ef0f1d8cf61 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/1 -------------------------------- In general it's preferable to avoid placing cpumasks on the stack, as for large values of NR_CPUS these can consume significant amounts of stack space and make stack overflows more likely. Use cpumask_first_and_and() to avoid the need for a temporary cpumask on the stack. Signed-off-by: Dawei Li <dawei.li@shingroup.cn> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20240416085454.3547175-6-dawei.li@shingroup.cn Signed-off-by: Hangfan Li <lihangfan@iscas.ac.cn>
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check patch done. log: https://jenkins.oerv.ac.cn/job/rvck-pipeline/job/check-patch/173/consoleFull |
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Kernel build failed! log:https://jenkins.oerv.ac.cn/job/rvck-pipeline/job/rvck-kernel-build/203/consoleFull |
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kunit test done. log:https://jenkins.oerv.ac.cn/job/rvck-pipeline/job/kunit-test/178/consoleFull |
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