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mainline inclusion from mainline-v6.11-rc1 commit 39494aec8a0454f9e8a68d2422d3bd4e5c5ee0c7 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/37 -------------------------------- Add RINTC affinity structure handler during parsing SRAT table. Signed-off-by: Haibo Xu <haibo1.xu@intel.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
driver inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/37 Reference: torvalds/linux@3a785e1 -------------------------------- The ACPI NUMA functions for the IA-64 architecture were implemented separately due to its unique hardware design. In a higher version, the kernel removed the IA-64 architecture code [1] and unify the ACPI NUMA implementation. However, to avoid the risks associated with extensive code modifications, we retained the IA-64 ACPI NUMA function definitions to ensure compatibility and stability. The acpi_numa_slit_init(), acpi_numa_memory_affinity_init() and acpi_parse_cfmws() functions will be used on platforms that support RISC-V ACPI_NUMA. [1] commit cf8e8658100d ("arch: Remove Itanium (IA-64) architecture") Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
driver inclusion category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/37 Reference: torvalds/linux@adc3e82 -------------------------------- x86/arm64/loongarch would select ACPI_NUMA by default and riscv would do the same thing, so change it to a hidden option and the select statements except for the X86_64_ACPI_NUMA can also go away. Suggested-by: Arnd Bergmann <arnd@arndb.de> Suggested-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Haibo Xu <haibo1.xu@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Huacai Chen <chenhuacai@loongson.cn> Acked-by: Will Deacon <will@kernel.org> Reviewed-by: Hanjun Guo <guohanjun@huawei.com> Link: https://lore.kernel.org/r/f1f96377b8ecd6e3183f28abf5c9ac21cb9855ea.1718268003.git.haibo1.xu@intel.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> [Since there is no sw_64 architecture in the upstream, changes were made to that architecture for the same purpose.] Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-v6.11-rc1 commit 5f76d4211ee44dcd9b2dc8a9065002bf8ecee81e category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/37 -------------------------------- There are lots of ACPI enabled systems that aren't NUMA and If the firmware didn't provide the SRAT/SLIT, then there will be a message "Failed to initialise from firmware" from arch_acpi_numa_init() which adding noise to the boot on all of those kind of systems. Replace the pr_info with pr_debug in arch_acpi_numa_init() to avoid it. Suggested-by: Sunil V L <sunilvl@ventanamicro.com> Signed-off-by: Haibo Xu <haibo1.xu@intel.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
mainline inclusion from mainline-v6.9-rc1 commit 8ec99b033147ef3bb8f0a560c24eb1baec3bc0be category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- The PLIC driver does not require very early initialization so convert it into a platform driver. After conversion, the PLIC driver is probed after CPUs are brought-up so setup cpuhp state after context handler of all online CPUs are initialized otherwise PLIC driver crashes for platforms with multiple PLIC instances. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240222094006.1030709-2-apatel@ventanamicro.com [Add bugfix patch authored by haijiao.liu bcc526e9d38a ("drivers: Fix an warning handling path in acpi_scan_clear_dep_fn()"). Otherwise, it will cause Pioneer(sg2042) to fail to boot. Tested by Mingzheng Xing <xingmingzheng@iscas.ac.cn>] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.9-rc1 commit 25d862e183d4efeb5e8b9843d783c90aaae4b14a category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Use dev_info(), dev_warn(), and dev_err() in-place of pr_info(), pr_warn(), and pr_err(). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240222094006.1030709-3-apatel@ventanamicro.com Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.9-rc1 commit b68d0ff529a939a118ec52f271be8cad5d99e79a category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Use devm_xyz() for allocations and mappings managed by the Linux device driver framework. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240222094006.1030709-4-apatel@ventanamicro.com Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.9-rc1 commit 6c725f33d67b53f2d302c2c4509deae953fc6ade category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- The RISC-V INTC irqdomain is always the parent irqdomain of SiFive PLIC so use riscv_get_intc_hwnode() to get the parent fwnode similar to other RISC-V drivers which use local interrupts. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240222094006.1030709-5-apatel@ventanamicro.com Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
…ilure mainline inclusion from mainline-v6.9-rc1 commit a15587277a246c388c83b1cd9cf7c1a868cd752f category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- The SiFive PLIC contexts should not be left dangling if irqdomain creation fails because plic_starting_cpu() can crash accessing unmapped registers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240222094006.1030709-6-apatel@ventanamicro.com Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
… plic_probe() mainline inclusion from mainline-v6.9-rc1 commit 95652106478030f54620b1f0d28f78ab110b3212 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- The SiFive PLIC driver needs to know the number of interrupts and contexts to complete initialization. Parse these details early in plic_probe() to avoid unnecessary memory allocations and register mappings if these details are not available. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240222094006.1030709-7-apatel@ventanamicro.com Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.9-rc1 commit abb7205794900503d6358ef1fb645373753a794d category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Now that PLIC driver is probed as a regular platform driver, the lock dependency validator complains about the safety of handler->enable_lock usage: [ 0.956775] Possible interrupt unsafe locking scenario: [ 0.956998] CPU0 CPU1 [ 0.957247] ---- ---- [ 0.957439] lock(&handler->enable_lock); [ 0.957607] local_irq_disable(); [ 0.957793] lock(&irq_desc_lock_class); [ 0.958021] lock(&handler->enable_lock); [ 0.958246] <Interrupt> [ 0.958342] lock(&irq_desc_lock_class); [ 0.958501] *** DEADLOCK *** To address above, use raw_spin_lock_irqsave/unlock_irqrestore() instead of raw_spin_lock/unlock(). Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240222094006.1030709-8-apatel@ventanamicro.com Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.10-rc1 commit a7fb69ffd7ce438a259b2f9fbcebc62f5caf2d4f category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- In general it's preferable to avoid placing cpumasks on the stack, as for large values of NR_CPUS these can consume significant amounts of stack space and make stack overflows more likely. Use cpumask_first_and_and() to avoid the need for a temporary cpumask on the stack. Signed-off-by: Dawei Li <dawei.li@shingroup.cn> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20240416085454.3547175-7-dawei.li@shingroup.cn Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.10-rc1 commit e306a894bd511804ba9db7c00ca9cc05b55df1f2 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Now that the PLIC uses a platform driver, the driver is probed later in the boot process, where interrupts from peripherals might already be pending. As a result, plic_handle_irq() may be called as early as the call to irq_set_chained_handler() completes. But this call happens before the per-context handler is completely set up, so there is a window where plic_handle_irq() can see incomplete per-context state and crash. Avoid this by delaying the call to irq_set_chained_handler() until all handlers from all PLICs are initialized. Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Anup Patel <anup@brainfault.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20240529215458.937817-1-samuel.holland@sifive.com Closes: https://lore.kernel.org/r/CAMuHMdVYFFR7K5SbHBLY-JHhb7YpgGMS_hnRWm8H0KD-wBo+4A@mail.gmail.com/ Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.11-rc1 commit 4d936f10ff80274841537a26d1fbfe9984de0ef9 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- The latest Linux RISC-V no longer boots on the Allwinner D1 platform because the sun4i_timer driver fails to get an interrupt from PLIC due to the recent conversion of the PLIC to a platform driver. Converting the sun4i timer to a platform driver does not work either because the D1 does not have a SBI timer available so early boot hangs. See the 'Closes:' link for deeper analysis. The real fix requires enabling the SBI time extension in the platform firmware (OpenSBI) and convert sun4i_timer into platform driver. Unfortunately, the real fix involves changing multiple places and can't be achieved in a short duration and aside of that requires users to update firmware. As a work-around, retrofit PLIC probing such that the PLIC is probed early only for the Allwinner D1 platform and probed as a regular platform driver for rest of the RISC-V platforms. In the process, partially revert some of the previous changes because the PLIC device pointer is not available in all probing paths. Fixes: e306a894bd51 ("irqchip/sifive-plic: Chain to parent IRQ after handlers are ready") Fixes: 8ec99b033147 ("irqchip/sifive-plic: Convert PLIC driver into a platform driver") Suggested-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/20240820034850.3189912-1-apatel@ventanamicro.com Closes: https://lore.kernel.org/lkml/20240814145642.344485-1-emil.renner.berthing@canonical.com/ Conflicts: drivers/irqchip/irq-sifive-plic.c [Context conflicts with 5fe176d ("irqchip/sifive-plic: Convert PLIC driver into a platform driver"). Tested by Mingzheng Xing <xingmingzheng@iscas.ac.cn>] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.12-rc1 commit 789befdfa3892957d36d20e6e90be05486e316c5 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- The functions defined in arm64 for ACPI support are required for RISC-V also. To avoid duplication, move these functions to common location. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Will Deacon <will@kernel.org> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-2-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
… probe mainline inclusion from mainline-v6.12-rc1 commit a9b8f337ea4eb66e4980f90bb73e8786e56cacfd category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Unlike OF framework, the irqchip probe using IRQCHIP_ACPI_DECLARE has no order defined. Depending on the Makefile is not a good idea. So, usually it is worked around by mandating only root interrupt controller probed using IRQCHIP_ACPI_DECLARE and other interrupt controllers are probed via cascade mechanism. However, this is also not a clean solution because if there are multiple root controllers (ex: RINTC in RISC-V which is per CPU) which need to be probed first, then the cascade will happen for every root controller. So, introduce an architecture specific weak function arch_sort_irqchip_probe() to order the probing of the interrupt controllers which can be implemented by different architectures as per their interrupt controller hierarchy. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-3-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.12-rc1 commit f7d7ccf92f2b9398781f791b4af1a74a9f65b5c3 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Add a new function for RISC-V to do architecture specific initialization similar to acpi_arm_init(). Some of the ACPI tables are architecture specific and there is no reason trying to find them on other architectures. So, add acpi_riscv_init() similar to acpi_arm_init(). Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-4-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [Resolve merge conflicts in drivers/acpi/riscv/Makefile] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.8-rc1 commit bd721b934323e4dcde892013a97e0e5674f4c884 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Find ACPI CSI-2 resource descriptors defined since ACPI 6.4 (for CSI-2 and camera configuration) in _CRS for all device objects in the given scope of the ACPI namespace that have them, identify the corresponding "remote endpoint" device objects for them and allocate memory for software nodes needed to create a DT-like data structure representing the CSI-2 connection graph for drivers. The code needed to populate these software nodes will be added by subsequent change sets. Link: https://uefi.org/specs/ACPI/6.5/06_Device_Configuration.html#camera-serial-interface-csi-2-connection-resource-descriptor Co-developed-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Tested-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.7-rc1 commit 2e57d10a6591560724b80a628235559571f4cb8d category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Address a long-standing "TBD" comment in the ACPI headers regarding the number of handles in struct acpi_handle_list. The number 10, which along with the comment dates back to 2.4.23, seems like it may have been arbitrarily chosen and isn't sufficient in all cases [1]. Finally change the code to dynamically determine the size of the handles table in struct acpi_handle_list and allocate it accordingly. Update the users of to struct acpi_handle_list to take the additional dynamic allocation into account. Link: https://lore.kernel.org/linux-acpi/20230809094451.15473-1-ivan.hu@canonical.com # [1] Co-developed-by: Vicki Pfau <vi@endrift.com> Signed-off-by: Vicki Pfau <vi@endrift.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [Resolve merge conflicts in drivers/acpi/thermal.c] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.7-rc5 commit 8f0b960a42badda7a2781e8a33564624200debc9 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- If a pointer to an uninitialized struct acpi_handle_list is passed to acpi_evaluate_reference() and it decides to bail out early, either because acpi_evaluate_object() fails, or because it produces invalid data, the handles pointer from the struct acpi_handle_list will be passed to kfree() and if it is not NULL, the kernel will crash on an attempt to free unallocated memory. Address this by moving the "end" label in acpi_evaluate_reference() to the end of the function, which is sufficient, because no cleanup is needed in that case. Fixes: 2e57d10a6591 ("ACPI: utils: Dynamically determine acpi_handle_list size") Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Tested-by: Woody Suwalski <terraluna977@gmail.com> [Resolve merge conflicts in drivers/acpi/utils.c] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.8-rc1 commit 87824da27b0aee399600d313667c1d812c2749d8 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- The code in acpi_evaluate_reference() can be improved in some ways without changing its observable behavior. Among other things: * None of the local variables in that function except for buffer needs to be initialized. * The element local variable is only used in the for () loop block, so it can be defined there. * Multiple checks can be combined. * Code duplication related to error handling can be eliminated. * Redundant inner parens can be dropped. Modify the function as per the above. No intentional functional impact. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.8-rc1 commit 6909e0f322b0527fee9fdc54685e6cad69008713 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- There are only 4 users of acpi_evaluate_reference() and none of them actually cares about the reason why it fails. All of them are only interested in whether or not it is successful, so it can return a bool value indicating that. Modify acpi_evaluate_reference() as per the observation above and update its callers accordingly so as to get rid of useless code and local variables. The observable behavior of the kernel is not expected to change after this modification of the code. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [Resolve merge conflicts in drivers/acpi/thermal.c] [Resolve merge conflicts in drivers/acpi/utils.c] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.8-rc1 commit 1feb042d4e9b30b3ec3363e557d2ba884485f835 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- It is somewhat better to use the size of the first array element for computing the size of the entire array than to rely on the array element data type definition knowledge and the former is also consistent with the array allocation in acpi_evaluate_reference(), so modify the code accordingly. No intentional functional impact. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.8-rc1 commit 4c660ffef34b7d645ae3144369bc50257f295212 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Fix inadvertently introduced white space damage in the struct acpi_handle_list definition. No functional impact. Fixes: 2e57d10a6591 ("ACPI: utils: Dynamically determine acpi_handle_list size") Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.12-rc1 commit 76d749c58f4c6dd333cb8ea515373f7c8df96e78 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Some architectures like RISC-V will use implicit dependencies like GSI map to create dependencies between interrupt controller and devices. To support doing that, the function which creates the dependency, is refactored bit and made public so that dependency can be added from outside of scan.c as well. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-5-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [Resolve merge conflicts in include/acpi/acpi_bus.h] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.12-rc1 commit 15f210f43e95ffaf87858c6d75339afeebbf8f5c category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- RISC-V PLIC and APLIC will have dependency from devices using GSI. So, add these devices to the honor list. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-6-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [Resolve merge conflicts in drivers/acpi/scan.c] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.12-rc1 commit 8cf252737b418c311d1016b0a7956407a235bb8d category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Some architectures like RISC-V need to add dependencies without explicit _DEP. Define a weak function which can be implemented by the architecture. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-7-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.12-rc1 commit 21734d29f84ad610dbafdca5f4c1bf7ecceeb2fb category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Add the IRQ model for RISC-V INTC so that acpi_set_irq_model can use this for RISC-V. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-8-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [Resolve merge conflicts in drivers/acpi/bus.c] [Resolve merge conflicts in include/linux/acpi.h] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.12-rc1 commit 2cb9155d116c4d9dd7610139a876d123b75924ef category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- RISC-V platforms need to use dependencies between PCI host bridge, Link devices and the interrupt controllers to ensure probe order. The dependency is like below. Interrupt controller <-- Link Device <-- PCI Host bridge. If there is no dependency between Link device and PCI Host Bridge, then PCI devices may be probed prior to Link devices. If a PCI device is probed before its Link device, we won't be able to find its INTx mapping. So, add the link device's HID to dependency honor list and clear the dependency after probe is done so that the dependent devices are unblocked to probe. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-9-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from mainline-v6.12-rc1 commit 01415e78cf724c3080846471f4b2accfe79ace81 category: feature bugzilla: https://github.com/RVCK-Project/rvck-olk/issues/40 -------------------------------- Replace the dummy implementation for PCI related functions with actual implementation. This needs ECAM and MCFG CONFIG options to be enabled for RISC-V. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Tested-by: Björn Töpel <bjorn@rivosinc.com> Link: https://patch.msgid.link/20240812005929.113499-10-sunilvl@ventanamicro.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> [Resolve merge conflicts in arch/riscv/Kconfig] Signed-off-by: haijiao.liu <haijiao.liu@sophgo.com>
mainline inclusion from Linux 6.6-rc6 commit 41182cc6f507011a2e6c82657779e451ed9942bb category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- We extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zfa extension for Guest/VM. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.6-rc5 commit d808f0b1be4888a87524164bc7dad2242734de38 category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- The SEED CSR access from VS/VU mode (guest) will always trap to HS-mode (KVM) when Zkr extension is available to the Guest/VM. Forward this CSR access to KVM user space so that it can be emulated based on the method chosen by VMM. Fixes: f370b4e668f0 ("RISC-V: KVM: Allow scalar crypto extensions for Guest/VM") Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.6-rc6 commit f943ebe2ec26272d71f9c7643ec667c616419bb1 category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Ztso extension for Guest/VM. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.6-rc6 commit 77fc0bfa43f83c1080b35a4915c767cf2c4979ff category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zacas extension for Guest/VM. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.6-rc6 commit fb2a3d63efefe6bd3718201daba479f4339bb4bf category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zimop extension for Guest/VM. Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.6-rc6 commit d964e8f2ae65dcc088345332d479d4fcc5a1d757 category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zca, Zcf, Zcd and Zcb extensions for Guest/VM. Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.6-rc6 commit 29cf9b803e6e9f1421f090478e624ca4c637c835 category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zcmop extension for Guest/VM. Signed-off-by: Clément Léger <cleger@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.6-rc6 commit 86d6a86e59e3aa425d829a935c0d92388e4fe55b category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- When a guest traps on wrs.nto, call kvm_vcpu_on_spin() to attempt to yield to the lock holding VCPU. Also extend the KVM ISA extension ONE_REG interface to allow KVM userspace to detect and enable the Zawrs extension for the Guest/VM. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.12-rc5 commit 1851e7836212c76bebb6944bb1541ddcccbea535 category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- The interface for controlling pointer masking in VS-mode is henvcfg.PMM, which is part of the Ssnpm extension, even though pointer masking in HS-mode is provided by the Smnpm extension. As a result, emulating Smnpm in the guest requires (only) Ssnpm on the host. The guest configures Smnpm through the SBI Firmware Features extension, which KVM does not yet implement, so currently the ISA extension has no visible effect on the guest, and thus it cannot be disabled. Ssnpm is configured using the senvcfg CSR within the guest, so that extension cannot be hidden from the guest without intercepting writes to the CSR. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.13-rc1 commit 97eccf7db4f2e5e59d16bca45f7803ae3aeff6e1 category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- We extend the KVM ISA extension ONE_REG interface to allow VMM tools to detect and enable Svade and Svadu extensions for Guest/VM. Since the henvcfg.ADUE is read-only zero if the menvcfg.ADUE is zero, the Svadu extension is available for Guest/VM and the Svade extension is allowed to disabledonly when arch_has_hw_pte_young() is true. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.13-rc5 commit 0f891585971648a07e8b0c155e5b3eb697601d9d category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Svvptc extension for Guest/VM. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.13-rc6 commit 679e132c0ae2c34b425f32fb1a59fc04c6dc87cb category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Zabha extension for Guest/VM. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from Linux 6.13-rc6 commit 79be257b579e72ae7c5aeb942700a449d467405f category: feature bugzilla: RVCK-Project/rvck#79 -------------------------------- Extend the KVM ISA extension ONE_REG interface to allow KVM user space to detect and enable Ziccrse extension for Guest/VM. Signed-off-by: Quan Zhou <zhouquan@iscas.ac.cn> Signed-off-by: Anup Patel <anup@brainfault.org> Signed-off-by: yechao-w <wang.yechao255@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from mainline-v6.6-rc2 commit c6f4a90022524d06f6d9de323b1757031dcf0c26 category: feature bugzilla: RVCK-Project/rvck#90 -------------------------------- The arch_spin_value_unlocked() of ticket-lock would cause the compiler to generate inefficient asm code in riscv architecture because of unnecessary memory access to the contended value. Before the patch: void lockref_get(struct lockref *lockref) { 78: fd010113 add sp,sp,-48 7c: 02813023 sd s0,32(sp) 80: 02113423 sd ra,40(sp) 84: 03010413 add s0,sp,48 0000000000000088 <.LBB296>: CMPXCHG_LOOP( 88: 00053783 ld a5,0(a0) After the patch: void lockref_get(struct lockref *lockref) { CMPXCHG_LOOP( 78: 00053783 ld a5,0(a0) After the patch, the lockref_get() could get in a fast path instead of the function's prologue. This is because ticket lock complex logic would limit compiler optimization for the spinlock fast path, and qspinlock won't. The caller of arch_spin_value_unlocked() could benefit from this change. Currently, the only caller is lockref. Signed-off-by: Guo Ren <guoren@kernel.org> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from mainline-v6.12 commit 6116e22ef33a8239f3d53bb25377e9ed733c4176 category: feature bugzilla: RVCK-Project/rvck#90 -------------------------------- The current fully-ordered cmpxchgXX() implementation results in: amocas.X.rl a5,a4,(s1) fence rw,rw This provides enough sync but we can actually use the following better mapping instead: amocas.X.aqrl a5,a4,(s1) Suggested-by: Andrea Parri <andrea@rivosinc.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from mainline-v6.12 commit f7bd2be7663c7de1dde27dadd352b2c3f4e19106 category: feature bugzilla: RVCK-Project/rvck#90 -------------------------------- Now that Zacas is supported in the kernel, let's use the double word atomic version of amocas to improve the SLUB allocator. Note that we have to select fixed registers, otherwise gcc fails to pick even registers and then produces a reserved encoding which fails to assemble. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from mainline-v6.12 commit 97ddab7fbea8fceb044108b64ba2ee2c96ff8dab category: feature bugzilla: RVCK-Project/rvck#90 -------------------------------- This adds runtime support for Zabha in xchg8/16() operations. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from mainline-v6.12 commit cbe82e140bb76e1aa9f808cc841654a25b70d4e5 category: feature bugzilla: RVCK-Project/rvck#90 -------------------------------- The arch_spinlock_t of qspinlock has contained the atomic_t val, which satisfies the ticket-lock requirement. Thus, unify the arch_spinlock_t into qspinlock_types.h. This is the preparation for the next combo spinlock. Signed-off-by: Guo Ren <guoren@kernel.org> Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from mainline-v6.12 commit 22c33321e260c8b4c1877b2cc0c4e26a0c74c23f category: feature bugzilla: RVCK-Project/rvck#90 -------------------------------- Add a separate ticket-lock.h to include multiple spinlock versions and select one at compile time or runtime. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
mainline inclusion from mainline-v6.12 commit ab83647fadae2f1f723119dc066b39a461d6d288 category: feature bugzilla: RVCK-Project/rvck#90 -------------------------------- In order to produce a generic kernel, a user can select CONFIG_COMBO_SPINLOCKS which will fallback at runtime to the ticket spinlock implementation if Zabha or Ziccrse are not present. Note that we can't use alternatives here because the discovery of extensions is done too late and we need to start with the qspinlock implementation because the ticket spinlock implementation would pollute the spinlock value, so let's use static keys. This is largely based on Guo's work and Leonardo reviews at [1]. Link: https://lore.kernel.org/linux-riscv/20231225125847.2778638-1-guoren@kernel.org/ [1] Signed-off-by: Guo Ren <guoren@kernel.org> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn> Signed-off-by: Yanteng Si <si.yanteng@linux.dev> Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
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开始测试 log: https://github.com/RVCK-Project/rvck-olk/actions/runs/19623396088 参数解析结果
测试完成 详细结果:RVCK result
Kunit Test Resultkunit test failed Check Patch Result
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开始测试 log: https://github.com/RVCK-Project/rvck-olk/actions/runs/19623396088 参数解析结果
测试完成 详细结果:RVCK result
Kunit Test Resultkunit test failed Check Patch Result
测试完成 详细结果:RVCK result
Kunit Test Resultkunit test failed Kernel Build ResultKernel build succeeded: RVCK-Project/rvck-olk/141/ 1fc2609b36d631468b2d0d18ae8f8d0d /srv/guix_result/4286623b0ccf1cc7eb0731b5846b68f74689fe59/Image LAVA Checkargs:
result:Lava check done! lava log: https://lava.oerv.ac.cn/scheduler/job/934 lava result count: [fail]: 19, [pass]: 1587, [skip]: 293 Check Patch Result
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This was referenced Mar 22, 2026
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Link: RVCK-Project/rvck#92