sync: rvck #231: 【backport】rva23特性的补充，包括zalasr等

Documentation/arch/riscv/hwprobe.rst

@@ -249,6 +249,9 @@ The following keys are defined:
        defined in the in the RISC-V ISA manual starting from commit e87412e621f1
        ("integrate Zaamo and Zalrsc text (#1304)").
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZALASR`: The Zalasr extension is supported as
+       frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
+
   * :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as
        defined in the in the RISC-V ISA manual starting from commit e87412e621f1
        ("integrate Zaamo and Zalrsc text (#1304)").
@@ -271,6 +274,13 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as
        ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZABHA`: The Zabha extension is supported as
+       ratified in commit 49f49c842ff9 ("Update to Rafified state") of
+       riscv-zabha.
+
+  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as
+       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated.  Returns similar values to
@@ -312,6 +322,23 @@ The following keys are defined:
 * :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
   represents the size of the Zicbom block in bytes.
 
+* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0`: A bitmask containing the
+  sifive vendor extensions that are compatible with the
+  :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
+
+  * SIFIVE
+
+    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor
+        extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
+	Extensions Specification.
+
+    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor
+        extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
+	Instruction Extensions Specification.
+
+* :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
+  represents the size of the Zicbop block in bytes.
+
 * :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the
      performance of misaligned vector accesses on the selected set of processors.
 

Documentation/devicetree/bindings/riscv/extensions.yaml

@@ -171,6 +171,11 @@ properties:
             memory types as ratified in the 20191213 version of the privileged
             ISA specification.
 
+        - const: zalasr
+          description: |
+            The standard Zalasr extension for load-acquire/store-release as frozen
+            at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
+
         - const: zba
           description: |
             The standard Zba bit-manipulation extension for address generation

arch/riscv/include/asm/hwcap.h

@@ -49,63 +49,65 @@
 #define RISCV_ISA_EXT_ZICSR		40
 #define RISCV_ISA_EXT_ZIFENCEI		41
 #define RISCV_ISA_EXT_ZIHPM		42
-#define RISCV_ISA_EXT_SMSTATEEN		43
-#define RISCV_ISA_EXT_ZICOND		44
-#define RISCV_ISA_EXT_ZBC		45
-#define RISCV_ISA_EXT_ZBKB		46
-#define RISCV_ISA_EXT_ZBKC		47
-#define RISCV_ISA_EXT_ZBKX		48
-#define RISCV_ISA_EXT_ZKND		49
-#define RISCV_ISA_EXT_ZKNE		50
-#define RISCV_ISA_EXT_ZKNH		51
-#define RISCV_ISA_EXT_ZKR		52
-#define RISCV_ISA_EXT_ZKSED		53
-#define RISCV_ISA_EXT_ZKSH		54
-#define RISCV_ISA_EXT_ZKT		55
-#define RISCV_ISA_EXT_ZVBB		56
-#define RISCV_ISA_EXT_ZVBC		57
-#define RISCV_ISA_EXT_ZVKB		58
-#define RISCV_ISA_EXT_ZVKG		59
-#define RISCV_ISA_EXT_ZVKNED		60
-#define RISCV_ISA_EXT_ZVKNHA		61
-#define RISCV_ISA_EXT_ZVKNHB		62
-#define RISCV_ISA_EXT_ZVKSED		63
-#define RISCV_ISA_EXT_ZVKSH		64
-#define RISCV_ISA_EXT_ZVKT		65
-#define RISCV_ISA_EXT_ZFH		66
-#define RISCV_ISA_EXT_ZFHMIN		67
-#define RISCV_ISA_EXT_ZIHINTNTL		68
-#define RISCV_ISA_EXT_ZVFH		69
-#define RISCV_ISA_EXT_ZVFHMIN		70
-#define RISCV_ISA_EXT_ZFA		71
-#define RISCV_ISA_EXT_ZTSO		72
-#define RISCV_ISA_EXT_ZACAS		73
-#define RISCV_ISA_EXT_ZVE32X		74
-#define RISCV_ISA_EXT_ZVE32F		75
-#define RISCV_ISA_EXT_ZVE64X		76
-#define RISCV_ISA_EXT_ZVE64F		77
-#define RISCV_ISA_EXT_ZVE64D		78
-#define RISCV_ISA_EXT_ZIMOP		79
-#define RISCV_ISA_EXT_ZCA		80
-#define RISCV_ISA_EXT_ZCB		81
-#define RISCV_ISA_EXT_ZCD		82
-#define RISCV_ISA_EXT_ZCF		83
-#define RISCV_ISA_EXT_ZCMOP		84
-#define RISCV_ISA_EXT_ZAWRS		85
-#define RISCV_ISA_EXT_SVVPTC		86
-#define RISCV_ISA_EXT_SMMPM		87
-#define RISCV_ISA_EXT_SMNPM		88
-#define RISCV_ISA_EXT_SSNPM		89
-#define RISCV_ISA_EXT_ZABHA		90
-#define RISCV_ISA_EXT_ZICCRSE		91
-#define RISCV_ISA_EXT_SVADE		92
-#define RISCV_ISA_EXT_SVADU		93
-#define RISCV_ISA_EXT_ZFBFMIN		94
-#define RISCV_ISA_EXT_ZVFBFMIN		95
-#define RISCV_ISA_EXT_ZVFBFWMA		96
-#define RISCV_ISA_EXT_ZAAMO		97
-#define RISCV_ISA_EXT_ZALRSC		98
-#define RISCV_ISA_EXT_ZICBOP            99
+#define RISCV_ISA_EXT_XTHEADVECTOR	43
+#define RISCV_ISA_EXT_SMSTATEEN		44
+#define RISCV_ISA_EXT_ZICOND		45
+#define RISCV_ISA_EXT_ZBC		46
+#define RISCV_ISA_EXT_ZBKB		47
+#define RISCV_ISA_EXT_ZBKC		48
+#define RISCV_ISA_EXT_ZBKX		49
+#define RISCV_ISA_EXT_ZKND		50
+#define RISCV_ISA_EXT_ZKNE		51
+#define RISCV_ISA_EXT_ZKNH		52
+#define RISCV_ISA_EXT_ZKR		53
+#define RISCV_ISA_EXT_ZKSED		54
+#define RISCV_ISA_EXT_ZKSH		55
+#define RISCV_ISA_EXT_ZKT		56
+#define RISCV_ISA_EXT_ZVBB		57
+#define RISCV_ISA_EXT_ZVBC		58
+#define RISCV_ISA_EXT_ZVKB		59
+#define RISCV_ISA_EXT_ZVKG		60
+#define RISCV_ISA_EXT_ZVKNED		61
+#define RISCV_ISA_EXT_ZVKNHA		62
+#define RISCV_ISA_EXT_ZVKNHB		63
+#define RISCV_ISA_EXT_ZVKSED		64
+#define RISCV_ISA_EXT_ZVKSH		65
+#define RISCV_ISA_EXT_ZVKT		66
+#define RISCV_ISA_EXT_ZFH		67
+#define RISCV_ISA_EXT_ZFHMIN		68
+#define RISCV_ISA_EXT_ZIHINTNTL		69
+#define RISCV_ISA_EXT_ZVFH		70
+#define RISCV_ISA_EXT_ZVFHMIN		71
+#define RISCV_ISA_EXT_ZFA		72
+#define RISCV_ISA_EXT_ZTSO		73
+#define RISCV_ISA_EXT_ZACAS		74
+#define RISCV_ISA_EXT_ZVE32X		75
+#define RISCV_ISA_EXT_ZVE32F		76
+#define RISCV_ISA_EXT_ZVE64X		77
+#define RISCV_ISA_EXT_ZVE64F		78
+#define RISCV_ISA_EXT_ZVE64D		79
+#define RISCV_ISA_EXT_ZIMOP		80
+#define RISCV_ISA_EXT_ZCA		81
+#define RISCV_ISA_EXT_ZCB		82
+#define RISCV_ISA_EXT_ZCD		83
+#define RISCV_ISA_EXT_ZCF		84
+#define RISCV_ISA_EXT_ZCMOP		85
+#define RISCV_ISA_EXT_ZAWRS		86
+#define RISCV_ISA_EXT_SVVPTC		87
+#define RISCV_ISA_EXT_SMMPM		88
+#define RISCV_ISA_EXT_SMNPM		89
+#define RISCV_ISA_EXT_SSNPM		90
+#define RISCV_ISA_EXT_ZABHA		91
+#define RISCV_ISA_EXT_ZICCRSE		92
+#define RISCV_ISA_EXT_SVADE		93
+#define RISCV_ISA_EXT_SVADU		94
+#define RISCV_ISA_EXT_ZFBFMIN		95
+#define RISCV_ISA_EXT_ZVFBFMIN		96
+#define RISCV_ISA_EXT_ZVFBFWMA		97
+#define RISCV_ISA_EXT_ZAAMO		98
+#define RISCV_ISA_EXT_ZALRSC		99
+#define RISCV_ISA_EXT_ZICBOP            100
+#define RISCV_ISA_EXT_ZALASR		101
 
 #define RISCV_ISA_EXT_XLINUXENVCFG	127
 

arch/riscv/include/asm/hwprobe.h

@@ -1,14 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
 /*
- * Copyright 2023 Rivos, Inc
+ * Copyright 2023-2024 Rivos, Inc
  */
 
 #ifndef _ASM_HWPROBE_H
 #define _ASM_HWPROBE_H
 
 #include <uapi/asm/hwprobe.h>
 
-#define RISCV_HWPROBE_MAX_KEY 10
+#define RISCV_HWPROBE_MAX_KEY 15
 
 static inline bool riscv_hwprobe_key_is_valid(__s64 key)
 {
@@ -21,6 +21,9 @@ static inline bool hwprobe_key_is_bitmask(__s64 key)
 	case RISCV_HWPROBE_KEY_BASE_BEHAVIOR:
 	case RISCV_HWPROBE_KEY_IMA_EXT_0:
 	case RISCV_HWPROBE_KEY_CPUPERF_0:
+	case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
+	case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0:
+	case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0:
 		return true;
 	}
 

arch/riscv/include/asm/insn-def.h

@@ -179,6 +179,7 @@
 #define RV___RS1(v)		__RV_REG(v)
 #define RV___RS2(v)		__RV_REG(v)
 
+#define RV_OPCODE_AMO		RV_OPCODE(47)
 #define RV_OPCODE_MISC_MEM	RV_OPCODE(15)
 #define RV_OPCODE_OP_IMM	RV_OPCODE(19)
 #define RV_OPCODE_SYSTEM	RV_OPCODE(115)
@@ -208,6 +209,84 @@
 	__ASM_STR(.error "hlv.d requires 64-bit support")
 #endif
 
+#define LB_AQ(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(26),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LB_AQRL(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(27),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LH_AQ(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(26),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LH_AQRL(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(27),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LW_AQ(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(26),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LW_AQRL(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(27),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define SB_RL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(29),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SB_AQRL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(0), FUNC7(31),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SH_RL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(29),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SH_AQRL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(1), FUNC7(31),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SW_RL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(29),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SW_AQRL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(2), FUNC7(31),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#ifdef CONFIG_64BIT
+#define LD_AQ(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(26),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define LD_AQRL(dest, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(27),			\
+	       RD(dest), RS1(addr), __RS2(0))
+
+#define SD_RL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(29),			\
+	       __RD(0), RS1(addr), RS2(src))
+
+#define SD_AQRL(src, addr)					\
+	INSN_R(OPCODE_AMO, FUNC3(3), FUNC7(31),			\
+	       __RD(0), RS1(addr), RS2(src))
+#else
+#define LD_AQ(dest, addr)					\
+	__ASM_STR(.error "ld.aq requires 64-bit support")
+
+#define LD_AQRL(dest, addr)					\
+	__ASM_STR(.error "ld.aqrl requires 64-bit support")
+
+#define SD_RL(dest, addr)					\
+	__ASM_STR(.error "sd.rl requires 64-bit support")
+
+#define SD_AQRL(dest, addr)					\
+	__ASM_STR(.error "sd.aqrl requires 64-bit support")
+#endif
+
 #define SINVAL_VMA(vaddr, asid)					\
 	INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(11),		\
 	       __RD(0), RS1(vaddr), RS2(asid))

arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2025 MIPS.
+ */
+
+#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
+#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
+
+#include <linux/cpumask.h>
+#include <uapi/asm/hwprobe.h>
+
+#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS
+void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair, const struct cpumask *cpus);
+#else
+static inline void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair,
+						 const struct cpumask *cpus)
+{
+	pair->value = 0;
+}
+#endif
+
+#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_

arch/riscv/include/asm/vendor_extensions/sifive_hwprobe.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_HWPROBE_H
+#define _ASM_RISCV_VENDOR_EXTENSIONS_SIFIVE_HWPROBE_H
+
+#include <linux/cpumask.h>
+
+#include <uapi/asm/hwprobe.h>
+
+#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
+void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cpumask *cpus);
+#else
+static inline void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair,
+						   const struct cpumask *cpus)
+{
+	pair->value = 0;
+}
+#endif
+
+#endif

arch/riscv/include/asm/vendor_extensions/thead_hwprobe.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H
+#define _ASM_RISCV_VENDOR_EXTENSIONS_THEAD_HWPROBE_H
+
+#include <linux/cpumask.h>
+
+#include <uapi/asm/hwprobe.h>
+
+#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_THEAD
+void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpumask *cpus);
+#else
+static inline void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair,
+						  const struct cpumask *cpus)
+{
+	pair->value = 0;
+}
+#endif
+
+#endif