Skip to content

[Backport] Added SBI v3.0 PMU enhancements in KVM and perf driver#282

Open
yechao-w wants to merge 15 commits into
RVCK-Project:rvck-6.6from
yechao-w:sbi-v3
Open

[Backport] Added SBI v3.0 PMU enhancements in KVM and perf driver#282
yechao-w wants to merge 15 commits into
RVCK-Project:rvck-6.6from
yechao-w:sbi-v3

Conversation

@yechao-w
Copy link
Copy Markdown
Contributor

@yechao-w yechao-w commented May 20, 2026

issues: #281

一、功能介绍
SBI v3.0 规范为 PMU 章节增加了两项新改进
1）新增了一个 get_event_info 函数，用于批量查询事件可用性，而无需为每个事件单独调用 SBI。这有助于缩短启动时间。
2）raw event 扩展到56 bits（raw event v2）

二、补丁集合

补丁集 编号 Commit 信息 补丁一致性
前置依赖 1 f0c9363 perf/riscv-sbi: Add platform specific firmware event handling 一致
2 16d3b1a perf: RISC-V: Check standard event availability 一致
3 c625154 drivers/perf: riscv: Align errno for unsupported perf event 一致
4 fc58db9 drivers/perf: riscv: Fix Platform firmware event data 一致
5 2c206cd drivers/perf: riscv: Return error for default case 一致
6 3aff4cd drivers/perf: riscv: Do not allow invalid raw event config 一致
Added SBI v3.0 PMU enhancements in KVM and perf driver 1/8 8c8d0f0 drivers/perf: riscv: Add SBI v3.0 flag 一致
2/8 656ef2e drivers/perf: riscv: Add raw event v2 support 一致
3/8 190b741 RISC-V: KVM: Add support for Raw event v2 一致
4/8 adffbd0 drivers/perf: riscv: Implement PMU event info function 一致
5/8 880fcc3 drivers/perf: riscv: Export PMU event info function 一致
6/8 41f4d0c RISC-V: KVM: No need of explicit writable slot check 一致
7/8 e309fd1 RISC-V: KVM: Implement get event info function 一致
8/8 dbdadd9 RISC-V: KVM: Upgrade the supported SBI version to 3.0 一致
fix补丁 1 1c0180c RISC-V: KVM: Remove unnecessary 'ret' assignment 一致

三、测试验证
qemu riscv上，opensbi更新到v1.8版本。

  1. dmesg查看sbi版本
[root@tcg riscv]# dmesg |grep SBI
[    0.000000] SBI specification v3.0 detected
[    0.000000] SBI implementation ID=0x1 Version=0x10008
[    0.000000] SBI TIME extension detected
[    0.000000] SBI IPI extension detected
[    0.000000] SBI RFENCE extension detected
[    0.000000] SBI SRST extension detected
[    0.000000] SBI DBCN extension detected
[    0.000000] SBI FWFT extension detected
[    0.000000] SBI HSM extension detected

sbi version探测到为v3.0版本。

  1. sbi_pmu_test
[root@tcg riscv]# ./sbi_pmu_test 
SBI PMU basic test : PASS
SBI PMU event verification test : PASS
SBI PMU event verification with snapshot test : PASS
SBI PMU event verification with overflow test : PASS
  1. kvm虚拟机验证
[root@rv-kvm ~]# dmesg |grep -i sbi
[    0.000000] SBI specification v3.0 detected
[    0.000000] SBI implementation ID=0x3 Version=0x60666
[    0.000000] SBI TIME extension detected
[    0.000000] SBI IPI extension detected
[    0.000000] SBI RFENCE extension detected
[    0.000000] SBI SRST extension detected
[    0.000000] SBI DBCN extension detected
[    0.000000] SBI HSM extension detected

kvm虚拟机同样探测到sbi v3.0版本

mdchitale and others added 15 commits May 20, 2026 14:49
@mdchitale @yechao-w
perf/riscv-sbi: Add platform specific firmware event handling
014d369 
mainline inclusion
from mainline-6.12-rc1
commit f0c9363
category: feature
bugzilla: RVCK-Project#281

--------------------------------

The SBI v2.0 specification pointed to by the link below reserves the
event code 0xffff for platform specific firmware events. Update the driver
to be able to parse and program such events. The platform specific
firmware events must now be specified in the perf command as below:
perf stat -e rCxxx ...
where bits[63:62] = 0x3 of the event config indicate a platform specific
firmware event and xxx indicate the actual event code which is passed
as the event data.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Link: https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v2.0/riscv-sbi.pdf
Link: https://lore.kernel.org/r/20240812051109.6496-1-mchitale@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@SiFiveHolland @yechao-w
perf: RISC-V: Check standard event availability
b851fa1 
mainline inclusion
from mainline-6.10-rc7
commit 16d3b1a
category: feature
bugzilla: RVCK-Project#281

--------------------------------

The RISC-V SBI PMU specification defines several standard hardware and
cache events. Currently, all of these events are exposed to userspace,
even when not actually implemented. They appear in the `perf list`
output, and commands like `perf stat` try to use them.

This is more than just a cosmetic issue, because the PMU driver's .add
function fails for these events, which causes pmu_groups_sched_in() to
prematurely stop scheduling in other (possibly valid) hardware events.

Add logic to check which events are supported by the hardware (i.e. can
be mapped to some counter), so only usable events are reported to
userspace. Since the kernel does not know the mapping between events and
possible counters, this check must happen during boot, when no counters
are in use. Make the check asynchronous to minimize impact on boot time.

Fixes: e999143 ("RISC-V: Add perf platform driver based on SBI PMU extension")

Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20240628-misc_perf_fixes-v4-3-e01cfddcf035@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@yechao-w
drivers/perf: riscv: Align errno for unsupported perf event
ff99c20 
mainline inclusion
from mainline-6.12-rv2
commit c625154
category: feature
bugzilla: RVCK-Project#281

--------------------------------

RISC-V perf driver does not yet support PERF_TYPE_BREAKPOINT. It would
be more appropriate to return -EOPNOTSUPP or -ENOENT for this type in
pmu_sbi_event_map. Considering that other implementations return -ENOENT
for unsupported perf types, let's synchronize this behavior. Due to this
reason, a riscv bpf testcases perf_skip fail. Meanwhile, align that
behavior to the rest of proper place.

Signed-off-by: Pu Lehui <pulehui@huawei.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Fixes: 9b3e150 ("RISC-V: Add a simple platform driver for RISC-V legacy perf")
Fixes: 16d3b1a ("perf: RISC-V: Check standard event availability")
Fixes: e999143 ("RISC-V: Add perf platform driver based on SBI PMU extension")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20240831071520.1630360-1-pulehui@huaweicloud.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@atishp04 @yechao-w
drivers/perf: riscv: Fix Platform firmware event data
febafbf 
mainline inclusion
from mainline-6.13-rc7
commit fc58db9
category: feature
bugzilla: RVCK-Project#281

--------------------------------

Platform firmware event data field is allowed to be 62 bits for
Linux as uppper most two bits are reserved to indicate SBI fw or
platform specific firmware events.
However, the event data field is masked as per the hardware raw
event mask which is not correct.

Fix the platform firmware event data field with proper mask.

Fixes: f0c9363 ("perf/riscv-sbi: Add platform specific firmware event handling")

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241212-pmu_event_fixes_v2-v2-1-813e8a4f5962@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@atishp04 @yechao-w
drivers/perf: riscv: Return error for default case
9b88777 
mainline inclusion
from mainline-6.13-rc7
commit 2c206cd
category: feature
bugzilla: RVCK-Project#281

--------------------------------

If the upper two bits has an invalid valid (0x1), the event mapping
is not reliable as it returns an uninitialized variable.

Return appropriate value for the default case.

Fixes: f0c9363 ("perf/riscv-sbi: Add platform specific firmware event handling")

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241212-pmu_event_fixes_v2-v2-2-813e8a4f5962@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@atishp04 @yechao-w
drivers/perf: riscv: Do not allow invalid raw event config
f4db813 
mainline inclusion
from mainline-6.13-rc7
commit 3aff4cd
category: feature
bugzilla: RVCK-Project#281

--------------------------------

The SBI specification allows only lower 48bits of hpmeventX to be
configured via SBI PMU. Currently, the driver masks of the higher
bits but doesn't return an error. This will lead to an additional
SBI call for config matching which should return for an invalid
event error in most of the cases.

However, if a platform(i.e Rocket and sifive cores) implements a
bitmap of all bits in the event encoding this will lead to an
incorrect event being programmed leading to user confusion.

Report the error to the user if higher bits are set during the
event mapping itself to avoid the confusion and save an additional
SBI call.

Suggested-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20241212-pmu_event_fixes_v2-v2-3-813e8a4f5962@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@atishp04 @yechao-w
drivers/perf: riscv: Add SBI v3.0 flag
0c4002f 
mainline inclusion
from mainline-6.18-rc1
commit 8c8d0f0
category: feature
bugzilla: RVCK-Project#281

--------------------------------

There are new PMU related features introduced in SBI v3.0.
1. Raw Event v2 which allows mhpmeventX value to be 56 bit wide.
2. Get Event info function to do a bulk query at one shot.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-1-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@atishp04 @yechao-w
drivers/perf: riscv: Add raw event v2 support
5dcbc19 
mainline inclusion
from mainline-6.18-rc1
commit 656ef2e
category: feature
bugzilla: RVCK-Project#281

--------------------------------

SBI v3.0 introduced a new raw event type that allows wider
mhpmeventX width to be programmed via CFG_MATCH.

Use the raw event v2 if SBI v3.0 is available.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-2-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@atishp04 @yechao-w
RISC-V: KVM: Add support for Raw event v2
4c8684a 
mainline inclusion
from mainline-6.18-rc1
commit 190b741
category: feature
bugzilla: RVCK-Project#281

--------------------------------

SBI v3.0 introduced a new raw event type v2 for wider mhpmeventX
programming. Add the support in kvm for that.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-3-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@atishp04 @yechao-w
drivers/perf: riscv: Implement PMU event info function
08c8201 
mainline inclusion
from mainline-6.18-rc1
commit adffbd0
category: feature
bugzilla: RVCK-Project#281

--------------------------------

With the new SBI PMU event info function, we can query the availability
of the all standard SBI PMU events at boot time with a single ecall.
This improves the bootime by avoiding making an SBI call for each
standard PMU event. Since this function is defined only in SBI v3.0,
invoke this only if the underlying SBI implementation is v3.0 or higher.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-4-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@atishp04 @yechao-w
drivers/perf: riscv: Export PMU event info function
f423d9b 
mainline inclusion
from mainline-6.18-rc1
commit 880fcc3
category: feature
bugzilla: RVCK-Project#281

--------------------------------

The event mapping function can be used in event info function to find out
the corresponding SBI PMU event encoding during the get_event_info function
as well. Refactor and export it so that it can be invoked from kvm and
internal driver.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-5-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@atishp04 @yechao-w
RISC-V: KVM: No need of explicit writable slot check
7453738 
mainline inclusion
from mainline-6.18-rc1
commit 41f4d0c
category: feature
bugzilla: RVCK-Project#281

--------------------------------

There is not much value in checking if a memslot is writable explicitly
before a write as it may change underneath after the check. Rather, return
invalid address error when write_guest fails as it checks if the slot
is writable anyways.

Suggested-by: Sean Christopherson <seanjc@google.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-6-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@atishp04 @yechao-w
RISC-V: KVM: Implement get event info function
ec7ed86 
mainline inclusion
from mainline-6.18-rc1
commit e309fd1
category: feature
bugzilla: RVCK-Project#281

--------------------------------

The new get_event_info funciton allows the guest to query the presence
of multiple events with single SBI call. Currently, the perf driver
in linux guest invokes it for all the standard SBI PMU events. Support
the SBI function implementation in KVM as well.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-7-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@atishp04 @yechao-w
RISC-V: KVM: Upgrade the supported SBI version to 3.0
b435995 
mainline inclusion
from mainline-6.18-rc1
commit dbdadd9
category: feature
bugzilla: RVCK-Project#281

--------------------------------

Upgrade the SBI version to v3.0 so that corresponding features
can be enabled in the guest.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Paul Walmsley <pjw@kernel.org>
Link: https://lore.kernel.org/r/20250909-pmu_event_info-v6-8-d8f80cacb884@rivosinc.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@JohnsPony @yechao-w
RISC-V: KVM: Remove unnecessary 'ret' assignment
f4d5618 
mainline inclusion
from mainline-7.0-rc1
commit 1c0180c
category: feature
bugzilla: RVCK-Project#281

--------------------------------

If execution reaches "ret = 0" assignment in
kvm_riscv_vcpu_pmu_event_info() then it means
kvm_vcpu_write_guest() returned 0 hence ret is
already zero and does not need to be assigned 0.

Fixes: e309fd1 ("RISC-V: KVM: Implement get event info function")
Signed-off-by: Qiang Ma <maqianga@uniontech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20251229072530.3075496-1-maqianga@uniontech.com
Signed-off-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Wang Yechao <wang.yechao255@zte.com.cn>
@github-actions
Copy link
Copy Markdown

github-actions Bot commented May 20, 2026

开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/26150196599

参数解析结果
args value
repository RVCK-Project/rvck
head ref pull/282/head
base ref rvck-6.6
LAVA repo RVCK-Project/lavaci
LAVA hardware ['qemu', 'lpi4a', 'sg2042', 'k1']
LAVA Testcase path lava-testcases/common-test/ltp/ltp.yaml
need run job kunit-test,kernel-build,check-patch,lava-trigger

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

5 participants

@yechao-w @mdchitale @SiFiveHolland @atishp04 @JohnsPony