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[arch/x86] [WIP] Intel APX support #6423

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[arch/x86] [WIP] Intel APX support #6423

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@nullableVoidPtr
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@nullableVoidPtr nullableVoidPtr commented Feb 17, 2025 •
edited by emesare
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Currently a work in progress, unpolished, and needs a lot of testing against APX corpus binaries:

  • EGPRs
  • JMPABS
  • Push/Pop (untested)
    • PUSH2
    • PUSHP
    • POP2
    • POPP
  • CCMPSCC
  • CFCMOVCC
  • CTESTSCC
  • SETCC
  • Zero Upper
    • IMUL (untested)
    • SETCC (unimplemented)
  • New Data Destination

Resolves #5246

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xusheng6 commented Mar 10, 2025

@nullableVoidPtr thx for your work! Please let me know when you think the code is ready for reviewer!

@galenbwill galenbwill self-assigned this May 7, 2025
@galenbwill galenbwill added Arch: x86 Issues with the x86/x64 architecture plugin Type: Enhancement Component: Architecture Issue needs changes to an architecture plugin Impact: Low Issue is a papercut or has a good, supported workaround Effort: Medium Issues require < 1 month of work State: Blocked (Customer) Issue is blocked on waiting for a response from a customer labels May 7, 2025
@galenbwill galenbwill added this to the Future milestone May 7, 2025
@galenbwill galenbwill changed the title [arch/x86] Intel APX support [arch/x86] [WIP] Intel APX support May 7, 2025
@galenbwill galenbwill removed their assignment Aug 6, 2025
@psifertex psifertex marked this pull request as draft October 23, 2025 20:20
emesare
emesare reviewed Dec 1, 2025
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arch/x86/arch_x86.cpp
@@ -3435,6 +3462,23 @@ class X64Architecture: public X86CommonArchitecture
case XED_REG_R14W: return RegisterInfo(XED_REG_R14, 0, 2);
case XED_REG_R15W: return RegisterInfo(XED_REG_R15, 0, 2);

case XED_REG_R16W: return RegisterInfo(XED_REG_R16, 0, 1);
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@emesare emesare Dec 1, 2025

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return RegisterInfo(XED_REG_R16, 0, 1); -> return RegisterInfo(XED_REG_R16, 0, 2);

arch/x86/arch_x86.cpp
@@ -3472,6 +3516,23 @@ class X64Architecture: public X86CommonArchitecture
case XED_REG_R14D: return RegisterInfo(XED_REG_R14, 0, 4, true);
case XED_REG_R15D: return RegisterInfo(XED_REG_R15, 0, 4, true);

case XED_REG_R16D: return RegisterInfo(XED_REG_R16, 0, 1);
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return RegisterInfo(XED_REG_R16, 0, 1); -> return RegisterInfo(XED_REG_R16, 0, 4, true);

arch/x86/arch_x86.cpp
@@ -3518,6 +3579,23 @@ class X64Architecture: public X86CommonArchitecture
case XED_REG_R13: return RegisterInfo(XED_REG_R13, 0, 8);
case XED_REG_R14: return RegisterInfo(XED_REG_R14, 0, 8);
case XED_REG_R15: return RegisterInfo(XED_REG_R15, 0, 8);
case XED_REG_R16: return RegisterInfo(XED_REG_R16, 0, 1);
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return RegisterInfo(XED_REG_R16, 0, 1); -> return RegisterInfo(XED_REG_R16, 0, 8);

arch/x86/il.cpp
@@ -1870,6 +2265,10 @@ bool GetLowLevelILForInstruction(Architecture* arch, const uint64_t addr, LowLev
il.AddInstruction(il.Jump(ReadILOperand(il, xedd, addr, 0, 0)));
return false;

case XED_ICLASS_JMPABS:
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Should just be able to reuse existing case XED_ICLASS_JMP

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emesare commented Dec 1, 2025

The push / pop lifting looks fine on the binary https://github.com/user-attachments/files/23866882/apxbin.zip

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emesare commented Dec 1, 2025

image

CCMP also looks correct, the conditional CMP block and the DFV write block look fine.

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Arch: x86 Issues with the x86/x64 architecture plugin Component: Architecture Issue needs changes to an architecture plugin Effort: Medium Issues require < 1 month of work Impact: Low Issue is a papercut or has a good, supported workaround State: Blocked (Customer) Issue is blocked on waiting for a response from a customer

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Add support for Intel APX

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@nullableVoidPtr @xusheng6 @emesare @plafosse @galenbwill