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| 1 | +//===-- AIEUnallocatedSuperRegRewriter.cpp - Constrain tied sub-registers -===// |
| 2 | +// |
| 3 | +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +// (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates |
| 8 | +// |
| 9 | +//===----------------------------------------------------------------------===// |
| 10 | + |
| 11 | +#include "AIEBaseInstrInfo.h" |
| 12 | +#include "AIEBaseRegisterInfo.h" |
| 13 | +#include "AIESuperRegUtils.h" |
| 14 | + |
| 15 | +#include "llvm/ADT/MapVector.h" |
| 16 | +#include "llvm/ADT/SmallSet.h" |
| 17 | +#include "llvm/CodeGen/LiveDebugVariables.h" |
| 18 | +#include "llvm/CodeGen/LiveIntervals.h" |
| 19 | +#include "llvm/CodeGen/LiveRegMatrix.h" |
| 20 | +#include "llvm/CodeGen/LiveStacks.h" |
| 21 | +#include "llvm/CodeGen/MachineBlockFrequencyInfo.h" |
| 22 | +#include "llvm/CodeGen/MachineFunction.h" |
| 23 | +#include "llvm/CodeGen/MachineFunctionPass.h" |
| 24 | +#include "llvm/CodeGen/MachineInstr.h" |
| 25 | +#include "llvm/CodeGen/MachineInstrBuilder.h" |
| 26 | +#include "llvm/CodeGen/MachineOperand.h" |
| 27 | +#include "llvm/CodeGen/MachineRegisterInfo.h" |
| 28 | +#include "llvm/CodeGen/Passes.h" |
| 29 | +#include "llvm/CodeGen/SlotIndexes.h" |
| 30 | +#include "llvm/CodeGen/TargetInstrInfo.h" |
| 31 | +#include "llvm/CodeGen/TargetSubtargetInfo.h" |
| 32 | +#include "llvm/CodeGen/VirtRegMap.h" |
| 33 | +#include "llvm/Support/Debug.h" |
| 34 | +#include "llvm/Support/raw_ostream.h" |
| 35 | + |
| 36 | +using namespace llvm; |
| 37 | + |
| 38 | +#define DEBUG_TYPE "aie-ra-prepare" |
| 39 | + |
| 40 | +namespace { |
| 41 | + |
| 42 | +using RegRewriteInfo = std::vector<std::pair<Register, SmallSet<int, 8>>>; |
| 43 | + |
| 44 | +/// Split large unallocated compound registers into multiple new smaller vregs |
| 45 | +/// Than can be allocated to scalar registers. This pass will handle registers |
| 46 | +/// that were not allocated by Greedy so far. Currently, it is expected to |
| 47 | +/// process registers used in copies created during Greedy's LR split. |
| 48 | +/// Registers used in *2d or *3d instructions should be already allocated |
| 49 | +/// at this point. |
| 50 | +class AIEUnallocatedSuperRegRewriter : public MachineFunctionPass { |
| 51 | + |
| 52 | +public: |
| 53 | + static char ID; |
| 54 | + AIEUnallocatedSuperRegRewriter() : MachineFunctionPass(ID) {} |
| 55 | + |
| 56 | + void getAnalysisUsage(AnalysisUsage &AU) const override { |
| 57 | + AU.setPreservesCFG(); |
| 58 | + AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>(); |
| 59 | + AU.addRequired<VirtRegMapWrapperLegacy>(); |
| 60 | + AU.addPreserved<VirtRegMapWrapperLegacy>(); |
| 61 | + AU.addRequired<SlotIndexesWrapperPass>(); |
| 62 | + AU.addPreserved<SlotIndexesWrapperPass>(); |
| 63 | + AU.addRequired<LiveDebugVariablesWrapperLegacy>(); |
| 64 | + AU.addPreserved<LiveDebugVariablesWrapperLegacy>(); |
| 65 | + AU.addRequired<LiveStacksWrapperLegacy>(); |
| 66 | + AU.addPreserved<LiveStacksWrapperLegacy>(); |
| 67 | + AU.addRequired<LiveIntervalsWrapperPass>(); |
| 68 | + AU.addPreserved<LiveIntervalsWrapperPass>(); |
| 69 | + AU.addRequired<LiveRegMatrixWrapperLegacy>(); |
| 70 | + AU.addPreserved<LiveRegMatrixWrapperLegacy>(); |
| 71 | + MachineFunctionPass::getAnalysisUsage(AU); |
| 72 | + } |
| 73 | + |
| 74 | + bool runOnMachineFunction(MachineFunction &Fn) override; |
| 75 | +}; |
| 76 | + |
| 77 | +/// Identify unallocated virtual registers that can be split into subregisters. |
| 78 | +/// Returns a list of candidate registers with their rewritable subregister |
| 79 | +/// indices, excluding unused registers and those already assigned to physical |
| 80 | +/// registers. |
| 81 | +static RegRewriteInfo getRewriteCandidates(MachineRegisterInfo &MRI, |
| 82 | + const AIEBaseRegisterInfo &TRI, |
| 83 | + VirtRegMap &VRM) { |
| 84 | + RegRewriteInfo RegistersToRewrite; |
| 85 | + for (unsigned VRegIdx = 0, End = MRI.getNumVirtRegs(); VRegIdx != End; |
| 86 | + ++VRegIdx) { |
| 87 | + const Register Reg = Register::index2VirtReg(VRegIdx); |
| 88 | + |
| 89 | + // Ignore un-used or already allocated registers. |
| 90 | + if (MRI.reg_nodbg_empty(Reg) || VRM.hasPhys(Reg)) |
| 91 | + continue; |
| 92 | + |
| 93 | + const SmallSet<int, 8> RewritableSubRegs = |
| 94 | + AIESuperRegUtils::getRewritableSubRegs(Reg, MRI, TRI); |
| 95 | + |
| 96 | + if (RewritableSubRegs.empty()) |
| 97 | + continue; |
| 98 | + |
| 99 | + LLVM_DEBUG(dbgs() << "Candidate " << printReg(Reg, &TRI, 0, &MRI) << ":" |
| 100 | + << printRegClassOrBank(Reg, MRI, &TRI) << '\n'); |
| 101 | + |
| 102 | + RegistersToRewrite.push_back({Reg, RewritableSubRegs}); |
| 103 | + } |
| 104 | + |
| 105 | + LLVM_DEBUG(dbgs() << "Found " << RegistersToRewrite.size() |
| 106 | + << " candidate register(s) for rewriting\n"); |
| 107 | + |
| 108 | + return RegistersToRewrite; |
| 109 | +} |
| 110 | + |
| 111 | +/// Split candidate registers into independent virtual registers for each |
| 112 | +/// subregister. Each composite register is rewritten using its subregister |
| 113 | +/// indices, with live intervals and debug information updated accordingly. |
| 114 | +void rewriteCandidates(RegRewriteInfo &RegistersToRewrite, |
| 115 | + MachineRegisterInfo &MRI, const AIEBaseRegisterInfo &TRI, |
| 116 | + VirtRegMap &VRM, LiveRegMatrix &LRM, LiveIntervals &LIS, |
| 117 | + SlotIndexes &Indexes, LiveDebugVariables &DebugVars) { |
| 118 | + |
| 119 | + LLVM_DEBUG(dbgs() << "Rewriting " << RegistersToRewrite.size() |
| 120 | + << " candidate register(s)\n"); |
| 121 | + |
| 122 | + for (auto [VReg, SubRegs] : RegistersToRewrite) { |
| 123 | + LLVM_DEBUG(dbgs() << " Rewriting " << printReg(VReg, &TRI, 0, &MRI) |
| 124 | + << " into " << SubRegs.size() << " subregister(s)\n"); |
| 125 | + std::optional<Register> NoPhysReg = {}; |
| 126 | + AIESuperRegUtils::rewriteSuperReg(VReg, NoPhysReg, SubRegs, MRI, TRI, VRM, |
| 127 | + LRM, LIS, Indexes, DebugVars); |
| 128 | + } |
| 129 | +} |
| 130 | + |
| 131 | +bool AIEUnallocatedSuperRegRewriter::runOnMachineFunction(MachineFunction &MF) { |
| 132 | + LLVM_DEBUG(llvm::dbgs() << "*** Splitting unallocated super-registers: " |
| 133 | + << MF.getName() << " ***\n"); |
| 134 | + |
| 135 | + MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 136 | + VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM(); |
| 137 | + LiveRegMatrix &LRM = getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM(); |
| 138 | + LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS(); |
| 139 | + SlotIndexes &Indexes = getAnalysis<SlotIndexesWrapperPass>().getSI(); |
| 140 | + LiveDebugVariables &DebugVars = |
| 141 | + getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV(); |
| 142 | + auto &TRI = |
| 143 | + *static_cast<const AIEBaseRegisterInfo *>(MRI.getTargetRegisterInfo()); |
| 144 | + |
| 145 | + LLVM_DEBUG(dbgs() << "Identifying rewrite candidates...\n"); |
| 146 | + RegRewriteInfo RegistersToRewrite = getRewriteCandidates(MRI, TRI, VRM); |
| 147 | + |
| 148 | + if (RegistersToRewrite.empty()) { |
| 149 | + LLVM_DEBUG(dbgs() << "No candidates found, skipping rewrite\n"); |
| 150 | + return false; |
| 151 | + } |
| 152 | + |
| 153 | + LLVM_DEBUG(dbgs() << "Performing register rewrites...\n"); |
| 154 | + rewriteCandidates(RegistersToRewrite, MRI, TRI, VRM, LRM, LIS, Indexes, |
| 155 | + DebugVars); |
| 156 | + |
| 157 | + LLVM_DEBUG(dbgs() << "Successfully rewrote " << RegistersToRewrite.size() |
| 158 | + << " register(s)\n"); |
| 159 | + |
| 160 | + return !RegistersToRewrite.empty(); |
| 161 | +} |
| 162 | + |
| 163 | +} // end anonymous namespace |
| 164 | + |
| 165 | +char AIEUnallocatedSuperRegRewriter::ID = 0; |
| 166 | +char &llvm::AIEUnallocatedSuperRegRewriterID = |
| 167 | + AIEUnallocatedSuperRegRewriter::ID; |
| 168 | + |
| 169 | +INITIALIZE_PASS(AIEUnallocatedSuperRegRewriter, |
| 170 | + "aie-unallocated-superreg-rewrite", |
| 171 | + "AIE unallocated super-reg rewrite", false, false) |
| 172 | + |
| 173 | +llvm::FunctionPass *llvm::createAIEUnallocatedSuperRegRewriter() { |
| 174 | + return new AIEUnallocatedSuperRegRewriter(); |
| 175 | +} |
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