Single-cycle-RISC-processor-RTL-Design

Top level source file : "SingleCycleCPU.v"

List of Instructions Implemented

Type	Instructions implemented
R	ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND
I	JALR, LB, LH, LW, LBU, LHU, ADDI, SLTI, SLTIU, XORI, ORI, ANDI, SLLI, SRLI, SRAI
S	SB, SH, SW
B	BEQ, BNE, BLT, BGE, BLTU, BGEU
U	LUI, AUIPC
J	JAL