Skip to content

Pull requests: alexforencich/verilog-axis

New pull request New
6 Open 8 Closed
6 Open 8 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

Fix initialization of temp_m_axis_tvalid_reg to a single bit
#41 opened Aug 17, 2025 by LuminousXLB Loading…
Fix set_bus_skew constraint upper bound in axis_async_fifo.tcl
#33 opened Apr 15, 2024 by LukasVik Loading…
Add explicit python3 prefix to all python paths in test suite
#28 opened Dec 7, 2023 by dbarrie Loading…
Allow overriding RAM style in FIFO
#25 opened Oct 12, 2023 by tausen Loading…
2
Rename arbiter module to verilog_axis_arbiter
#21 opened Oct 13, 2022 by olofk Loading…
1
Fixes
#9 opened Oct 25, 2019 by olofk Loading…
ProTip! Updated in the last three days: updated:>2025-08-20.