COD Assignment

week1/PES2UG22EC115_Week1_Lab.md

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+# Program 1: 
+### Statement: Convert a 32-bit value from Little Endian to Big Endian format using RISC-V assembly
+
+### Name of file:
+PES2UG22EC115_Week1_Lab.s
+
+### Observation - Single Cycle
+- First we load the word data into register x11 using load word (lw). We define an iterating variable in x3 to know when to stop the loop. Using andi instruction to mask the MSB we obtain the least significant byte into register x12. 
+- We shift the extracted value to the left by required amount to get it towards MSB position and shift the original nummber to the right by 8 bits to remove the already extracted byte.
+- Using branch if not equal to zero we can stop the loop when iterating variable hits 0. Finally we do the final masking and addition to complete the reversal of bytes. We write back this value into another location in data memory to be able to compare little endian with big endian order of storing data.
+
+### Observation - Single Cycle
+- **Cycles:** 25
+- **Frequency:** 10.53 Hz
+- **CPI:** 1
+- **IPC:** 1
+
+### Observation - 5 Stage
+- **Cycles:** 33 
+- **Frequency:** 6.49 Hz
+- **CPI:** 1.32
+- **IPC:** 0.758
+
+### Register Mapping
+- **x11:** 0x00000012    Final value (Right Shifted in every iteration of loop)
+- **x12:** 0x00000034
+- **x14:** 0x78563400
+- **x15:** 0x78563412
+
+### Data Mapping
+- **0x10000000:** 0x12345678    Little Endian
+- **0x10000004:** 0x78563412    Big Endian
+
+### Snapshot
+![little2big](https://github.com/user-attachments/assets/76b08735-2096-4a9e-85e5-028c8bc85401)
+
+
+...
+
+
+
+# Program 2: 
+### Statement: Write an Assembly Program for addition of 2 64-bit numbers on RV32I
+
+### Name of file:
+PES2UG22EC115_Week1_Lab.s
+
+### Observation - Single Cycle
+- Store the 64-bit (double word) numbers into 4 32-bit registers in the order of MSB1, LSB1, MSB2, LSB2.
+- Load the LSB values of both numbers into 2 registers and add them. Check for carry using sltu instruction and store in another register. (sets value 1 if result value is greater  than either of the operands).
+- Perform the same steps for MSB of both numbers. FInally add the carry to the sum of MSB values. Check for carry in MSB addition using sltu to check for overflow in addition.
+- Result (MSB,LSB final value) is stored back into memory.
+
+### Observation - Single Cycle
+- **Cycles:** 13
+- **Frequency:** 6.21 Hz
+- **CPI:** 1
+- **IPC:** 1
+
+### Observation - 5 Stage
+- **Cycles:** 19 
+- **Frequency:** 5.85 Hz
+- **CPI:** 1.46
+- **IPC:** 0.684
+
+### Register Mapping
+- **x2:**  0x10000000
+- **x18:** 0x90000123
+- **x19:** 0xffffffff
+- **x20:** 0x90000122
+- **x21:** 0x00000001
+- **x22:** 0x80001234
+- **x23:** 0x90001234
+- **x24:** 0x10002468
+- **x25:** 0x00000001
+- **x26:** 0x10002469
+
+### Data Mapping
+- **0x10000000:** 0x80001234
+- **0x10000004:** 0x90000123
+- **0x10000008:** 0x90001234
+- **0x1000000c:** 0xffffffff
+- **0x10000014:** 0x90000122
+- **0x10000018:** 0x10002469
+
+### Snapshot
+![adding64bit](https://github.com/user-attachments/assets/9de90ea5-8e58-4133-acb2-2c5d3b8ceecd)
+
+...

week1/PES2UG22EC115_Week1_Lab.s

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+# PROGRAM 1
+# PROGRAM 1
+.data
+a: .word 0x12345678
+
+.text
+la x10,a
+lw x11,0(x10)
+addi x3,x0,3             # Iterating variable assigned to 3 because we are using word data
+back:
+    andi x12,x11,0xFF    # Masking the MSB to get the 2 least significant bytes 
+    add x14,x14,x12      # Adding the two numbers to join the bytes into 1 number
+    slli x14,x14,8       # Shifting left to move the above bytes to MSB position
+    srli x11,x11,8       # Shifting right to remove the LSB that has already been extracted
+    addi x3,x3,-1        # Modify iterating variable
+bnez x3,back
+andi x15,x11,0xFF        # Final byte 
+add x15,x14,x15 
+sw x15,4(x10)            # Writeback to data memory
+
+
+
+# PROGRAM 2
+.data
+a: .word 0x80001234 , 0x90000123 , 0x90001234 , 0xFFFFFFFF
+
+.text
+la x2, a
+lw x18,4(x2)
+lw x19,12(x2)
+add x20,x18,x19  # Adding LSB of both numbers
+sltu x21,x20,x18
+lw x22,0(x2)
+lw x23,8(x2)
+add x24,x22,x23  # Adding LSB of both numbers
+sltu x25,x24,x22 # Checks for overflow
+add x26,x24,x21  # Adds carry of LSB to MSB result
+sw x26,24(x2)    # MSB of result
+sw x20,20(x2)    # LSB of result

week10/alu_control.sv

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+module alu_control(
+    input logic [2:0]funct3,
+    input logic [6:0]funct7,
+    input logic [1:0]alu_op,
+    output logic [3:0]alu_control
+    );
+    always_comb
+    case(alu_op)
+        2'b10: begin
+            if(funct3[2:0]==0)
+            begin
+                if(funct7[5])
+                    alu_control=0110; //sub
+                else
+                    alu_control=0010; //add
+            end
+            else if(funct3[2:0]==3'b111)
+                alu_control=0000; //AND
+            else
+                alu_control=0001;  //OR
+        end
+        2'b00 : alu_control=0010;
+        2'b01 : alu_control=0110;
+        default : alu_control=0000;
+    endcase    
+endmodule

week10/control_unit.sv

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+module control_unit(
+    input logic [6:0] opcode,
+    input logic [2:0] funct3,
+    output logic [2:0] mem_control,
+    output logic [1:0] alu_op,
+    output logic reg_write,mem_read,mem_write,
+    output logic alu_src,
+    output logic mem_to_reg
+    );
+
+    always_comb
+    begin
+        alu_op = 2'b0;
+        alu_src = 1'b0;
+        mem_to_reg = 1'b0;
+        reg_write = 1'b0;
+        mem_read = 1'b0;
+        mem_write = 1'b0;
+        case(opcode)
+            7'b0110011 : begin  // R Type
+                reg_write = 1'b1;
+                alu_op = 2'b10;
+                end
+            7'b0000011 : begin  // Load
+                alu_src = 1'b1;
+                mem_read = 1'b1;
+                mem_to_reg = 1'b1;
+                reg_write = 1'b1;
+                alu_op = 2'b00;
+                case(funct3)
+					3'b000: mem_control = 3'b000; // LB
+					3'b001: mem_control = 3'b001; // LH
+					3'b010: mem_control = 3'b010; // LW
+					3'b100: mem_control = 3'b011; // LBU
+					3'b101: mem_control = 3'b100; // LHU
+					default: mem_control = 3'bX;  // Malformed instruction
+				endcase
+                end
+            7'b0100011 : begin  // Store
+                alu_src = 1'b1;
+                alu_op = 2'b00;
+                mem_write = 1'b1;
+                end
+            7'b1100011 : begin  //  Branch
+                mem_to_reg = 1'bx;
+                end
+        endcase
+     end                   
+endmodule

week2/PES2UG22EC115_Week2_Lab.md

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+# Program 1a: 
+### Statement: Write an Assembly Program for addition of 2 words
+
+### Name of file:
+PES2UG22EC115_Week2_Lab.s
+
+### Observation - Explanation
+- Two word-sized values are defined and stored in memory. We access data memory locations using physical address (Base Address + Immediate Offset)
+- Values are loaded into saved registers using load word (lw), added together, and the result is stored back in destination register.
+- Result stored in destination register is stored into data memory using store word (sw) instruction.
+
+### Observation - Single Cycle
+- **Cycles:** 6
+- **Frequency:** 6.45 Hz
+- **CPI:** 1
+- **IPC:** 1
+
+### Observation - 5 Stage
+- **Cycles:** 11
+- **Frequency:** 6.67 Hz
+- **CPI:** 1.83
+- **IPC:** 0.545
+
+### Register Mapping
+- **x18:** 0x80001234
+- **x19:** 0x90000123
+- **x20:** 0x10001357
+
+### Data Mapping
+- **0x10000008:** 0x10001357
+- **0x10000004:** 0x90000123
+- **0x10000000:** 0x80001234
+
+### Snapshot
+![word_addi](https://github.com/user-attachments/assets/757aab2f-d554-4949-9b1a-d517bc421745)
+
+# Program 1b: 
+### Statement: Write an Assembly Program for addition of 2 half words
+
+### Name of file:
+PES2UG22EC115_Week2_Lab.s
+
+### Observation - Explanation
+- Two 16-bit values are defined and stored in memory. We access data memory locations using physical address (Base Address + Immediate Offset)
+- Values are loaded into saved registers using load halfword (lh), added together, and the result is stored back in destination register.
+- Result stored in destination register is stored into data memory using store half-word (sh) instruction.
+
+### Observation - Single Cycle
+- **Cycles:** 6
+- **Frequency:** 6.33 Hz
+- **CPI:** 1
+- **IPC:** 1
+
+### Observation - 5 Stage
+- **Cycles:** 11
+- **Frequency:** 6.49 Hz
+- **CPI:** 1.83
+- **IPC:** 0.545
+
+### Register Mapping
+- **x18:** 0x000061a8
+- **x19:** 0x00000350
+- **x20:** 0x000064f8
+
+### Data Mapping
+- **0x10000004:** 0x000064f8
+- **0x10000000:** 0x035061a8
+
+### Snapshot
+![half_addi](https://github.com/user-attachments/assets/74abd484-3d3b-4eb3-a821-642cca698b6c)
+
+
+# Program 1c: 
+### Statement: Write an Assembly Program for addition of 2 bytes
+
+### Name of file:
+PES2UG22EC115_Week2_Lab.s
+
+### Observation - Explanation
+- Two byte (8-bit) values are defined and stored in memory. We access data memory locations using physical address (Base Address + Immediate Offset)
+- Values are loaded into saved registers using load halfword (lb), added together, and the result is stored back in destination register.
+- Result stored in destination register is stored into data memory using store half-word (sb) instruction.
+
+### Observation - Single Cycle
+- **Cycles:** 6
+- **Frequency:** 6.02 Hz
+- **CPI:** 1
+- **IPC:** 1
+
+### Observation - 5 Stage
+- **Cycles:** 11
+- **Frequency:** 6.58 Hz
+- **CPI:** 1.83
+- **IPC:** 0.545
+
+### Register Mapping
+- **x18:** 0x00000006
+- **x19:** 0x00000002
+- **x20:** 0x00000008
+
+### Data Mapping
+- **0x10000000:** 0x00080206
+
+### Snapshot
+![byte_addi](https://github.com/user-attachments/assets/acb0c159-0a62-4e66-a67a-55e2ded76fc9)
+
+# Program 2: 
+### Statement: Write an Assembly program for calculating x = (y + m) - (L - D) + (Z + C) - D, where x, y, m, L, D, Z, C are elements of 32-bits wide
+
+### Name of file:
+PES2UG22EC115_Week2_Lab.s
+
+### Observation - Explanation
+-
+
+### Observation - Single Cycle
+- **Cycles:** 12
+- **Frequency:** 6.06 Hz
+- **CPI:** 1
+- **IPC:** 1
+
+### Observation - 5 Stage
+- **Cycles:** 16
+- **Frequency:** 5.56 Hz
+- **CPI:** 1.33
+- **IPC:** 0.75
+
+### Register Mapping
+- **x6:** `0x0000000a`
+- **x7:** `0x00000005`
+- **x8:** `0x00000014`
+- **x9:** `0x00000003`
+- **x10:** `0x0000000f`
+- **x11:** `0x00000008`
+- **x12:** `0x0000000f`
+- **x13:** `0x00000011`
+- **x14:** `0xfffffffe`
+- **x15:** `0x00000017`
+- **x16:** `0x00000015`
+- **x17:** `0x00000012`
+
+
+### Snapshot
+![eqnprob](https://github.com/user-attachments/assets/ac9e0fea-574d-444a-b8ad-29e72a1de6a4)