adrv9371x: kcu105/zc706/zcu102: Replace dacfifo with data_offload

docs/projects/adrv9371x/index.rst

@@ -162,6 +162,7 @@ axi_adrv9009_rx_jesd      0x44AA_0000     0x84AA_0000
 axi_adrv9009_rx_os_jesd   0x44AB_0000     0x84AB_0000
 axi_adrv9009_rx_dma       0x7C40_0000     0x9C40_0000
 axi_adrv9009_tx_dma       0x7C42_0000     0x9C42_0000
+ad9371_data_offload       0x7C43_0000     0x9C43_0000
 axi_adrv9009_rx_os_dma    0x7C44_0000     0x9C44_0000
 axi_adrv9009_rx_clkgen    0x43C1_0000     0x83C1_0000
 axi_adrv9009_tx_clkgen    0x43C0_0000     0x83C0_0000
@@ -416,12 +417,12 @@ HDL related
    * - UTIL_CPACK2
      - :git-hdl:`library/util_pack/util_cpack2`
      - :ref:`util_upack2`
-   * - AXI_DACFIFO
-     - :git-hdl:`library/xilinx/axi_dacfifo`
-     - :ref:`util_axis_fifo`
-   * - UTIL_DACFIFO
-     - :git-hdl:`library/util_dacfifo`
-     - :ref:`util_rfifo`
+   * - DATA_OFFLOAD
+     - :git-hdl:`library/data_offload`
+     - :ref:`data_offload`
+   * - UTIL_DO_RAM
+     - :git-hdl:`library/util_do_ram`
+     - :ref:`data_offload`
    * - AXI_CLKGEN
      - :git-hdl:`library/axi_clkgen`
      - :ref:`axi_clkgen`

projects/adrv9371x/common/adrv9371x_bd.tcl

@@ -41,18 +41,17 @@ set RX_OS_SAMPLE_WIDTH 16                                    ; # N/NP
 set RX_OS_SAMPLES_PER_CHANNEL [expr $RX_OS_NUM_OF_LANES * 32 / \
                                    ($RX_OS_NUM_OF_CONVERTERS * $RX_OS_SAMPLE_WIDTH)] ;  # L * 32 / (M * N)
 
-set dac_fifo_name axi_ad9371_dacfifo
+set dac_offload_name ad9371_data_offload
 set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
 set dac_dma_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
 
 source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
 source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
+source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
 
 # ad9371
 
 create_bd_port -dir I ref_clk
-
-create_bd_port -dir I dac_fifo_bypass
 create_bd_port -dir I adc_fir_filter_active
 create_bd_port -dir I dac_fir_filter_active
 
@@ -102,7 +101,16 @@ ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_2D_TRANSFER 0
 ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
 ad_ip_parameter axi_ad9371_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY
 
-ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width
+ad_data_offload_create $dac_offload_name \
+                       1 \
+                       $dac_offload_type \
+                       $dac_offload_size \
+                       $dac_dma_data_width \
+                       $dac_data_width \
+                       $plddr_offload_axi_data_width
+
+ad_ip_parameter $dac_offload_name/i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0
+ad_connect $dac_offload_name/sync_ext GND
 
 # adc peripherals
 
@@ -254,10 +262,6 @@ for {set i 0} {$i < $MAX_RX_OS_NUM_OF_LANES} {incr i} {
   ad_xcvrpll  axi_ad9371_rx_os_xcvr/up_pll_rst util_ad9371_xcvr/up_cpll_rst_$ch
 }
 
-# dma clock & reset
-
-ad_connect  $sys_dma_reset axi_ad9371_dacfifo/dma_rst
-
 # connections (dac)
 
 ad_connect  axi_ad9371_tx_clkgen/clk_0 tx_ad9371_tpl_core/link_clk
@@ -266,8 +270,14 @@ ad_connect  axi_ad9371_tx_jesd/tx_data tx_ad9371_tpl_core/link
 ad_connect  axi_ad9371_tx_clkgen/clk_0 util_ad9371_tx_upack/clk
 ad_connect  ad9371_tx_device_clk_rstgen/peripheral_reset util_ad9371_tx_upack/reset
 
-ad_connect  axi_ad9371_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
-ad_connect  ad9371_tx_device_clk_rstgen/peripheral_reset axi_ad9371_dacfifo/dac_rst
+ad_connect  $sys_dma_clk $dac_offload_name/s_axis_aclk
+ad_connect  $sys_dma_resetn $dac_offload_name/s_axis_aresetn
+ad_connect  $sys_dma_clk axi_ad9371_tx_dma/m_axis_aclk
+ad_connect  $sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
+
+ad_connect  axi_ad9371_tx_clkgen/clk_0 $dac_offload_name/m_axis_aclk
+ad_connect  ad9371_tx_device_clk_rstgen/peripheral_aresetn $dac_offload_name/m_axis_aresetn
+ad_connect  util_ad9371_tx_upack/s_axis $dac_offload_name/m_axis
 
 ad_connect tx_fir_interpolator/aclk axi_ad9371_tx_clkgen/clk_0
 
@@ -295,21 +305,9 @@ if {$TX_NUM_OF_CONVERTERS <= 2} {
 
 ad_connect  tx_fir_interpolator/active dac_fir_filter_active
 
-# TODO: Add streaming AXI interface for DAC FIFO
-ad_connect  util_ad9371_tx_upack/s_axis_valid VCC
-ad_connect  util_ad9371_tx_upack/s_axis_ready axi_ad9371_dacfifo/dac_valid
-ad_connect  util_ad9371_tx_upack/s_axis_data axi_ad9371_dacfifo/dac_data
-
-ad_connect  $sys_dma_clk axi_ad9371_dacfifo/dma_clk
-ad_connect  $sys_dma_clk axi_ad9371_tx_dma/m_axis_aclk
-ad_connect  axi_ad9371_dacfifo/dma_valid axi_ad9371_tx_dma/m_axis_valid
-ad_connect  axi_ad9371_dacfifo/dma_data axi_ad9371_tx_dma/m_axis_data
-ad_connect  axi_ad9371_dacfifo/dma_ready axi_ad9371_tx_dma/m_axis_ready
-ad_connect  axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
-ad_connect  axi_ad9371_dacfifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
-ad_connect  axi_ad9371_dacfifo/dac_dunf tx_ad9371_tpl_core/dac_dunf
-ad_connect  axi_ad9371_dacfifo/bypass dac_fifo_bypass
-ad_connect  $sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
+ad_connect  $dac_offload_name/s_axis axi_ad9371_tx_dma/m_axis
+ad_connect  $dac_offload_name/init_req axi_ad9371_tx_dma/m_axis_xfer_req
+ad_connect  tx_ad9371_tpl_core/dac_dunf util_ad9371_tx_upack/fifo_rd_underflow
 
 # connections (adc)
 
@@ -371,6 +369,7 @@ ad_cpu_interconnect 0x44A80000 axi_ad9371_tx_xcvr
 ad_cpu_interconnect 0x43C00000 axi_ad9371_tx_clkgen
 ad_cpu_interconnect 0x44A90000 axi_ad9371_tx_jesd
 ad_cpu_interconnect 0x7c420000 axi_ad9371_tx_dma
+ad_cpu_interconnect 0x7c430000 $dac_offload_name
 ad_cpu_interconnect 0x44A60000 axi_ad9371_rx_xcvr
 ad_cpu_interconnect 0x43C10000 axi_ad9371_rx_clkgen
 ad_cpu_interconnect 0x44AA0000 axi_ad9371_rx_jesd

projects/adrv9371x/kcu105/Makefile

@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -8,13 +8,14 @@ PROJECT_NAME := adrv9371x_kcu105
 
 M_DEPS += ../common/adrv9371x_bd.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
-M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
 M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc
 M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_mig.tcl
 M_DEPS += ../../common/kcu105/kcu105_system_lutram_constr.xdc
 M_DEPS += ../../common/kcu105/kcu105_system_constr.xdc
 M_DEPS += ../../common/kcu105/kcu105_system_bd.tcl
+M_DEPS += ../../common/xilinx/data_offload_bd.tcl
+M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
 M_DEPS += ../../../library/util_cdc/sync_bits.v
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 M_DEPS += ../../../library/common/util_pulse_gen.v
@@ -24,14 +25,16 @@ M_DEPS += ../../../library/common/ad_bus_mux.v
 LIB_DEPS += axi_clkgen
 LIB_DEPS += axi_dmac
 LIB_DEPS += axi_sysid
+LIB_DEPS += data_offload
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
 LIB_DEPS += jesd204/axi_jesd204_rx
 LIB_DEPS += jesd204/axi_jesd204_tx
 LIB_DEPS += jesd204/jesd204_rx
 LIB_DEPS += jesd204/jesd204_tx
 LIB_DEPS += sysid_rom
-LIB_DEPS += util_dacfifo
+LIB_DEPS += util_do_ram
+LIB_DEPS += util_hbm
 LIB_DEPS += util_pack/util_cpack2
 LIB_DEPS += util_pack/util_upack2
 LIB_DEPS += xilinx/axi_adxcvr

projects/adrv9371x/kcu105/system_bd.tcl

@@ -1,16 +1,16 @@
 ###############################################################################
-## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-## FIFO depth is 8Mb - 500k samples
-set dac_fifo_address_width 16
-
-## NOTE: With this configuration the #36Kb BRAM utilization is at ~68%
+## Offload attributes
+set dac_offload_type 0                   ; ## BRAM
+set dac_offload_size [expr 1*1024*1024]  ; ## 1 MB
+set plddr_offload_axi_data_width 0
 
 source $ad_hdl_dir/projects/common/kcu105/kcu105_system_bd.tcl
 source $ad_hdl_dir/projects/common/kcu105/kcu105_system_mig.tcl
-source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
+source ../common/adrv9371x_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
 #system ID
@@ -27,14 +27,13 @@ S=$ad_project_params(TX_JESD_S)\
 RX_OS:M=$ad_project_params(RX_OS_JESD_M)\
 L=$ad_project_params(RX_OS_JESD_L)\
 S=$ad_project_params(RX_OS_JESD_S)\
-DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
+DAC_OFFLOAD:TYPE=$dac_offload_type\
+SIZE=$dac_offload_size"
 
 sysid_gen_sys_init_file $sys_cstring
 
 ad_ip_parameter axi_ddr_cntrl CONFIG.ADDN_UI_CLKOUT3_FREQ_HZ 200
 
-source ../common/adrv9371x_bd.tcl
-
 ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 80
 ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_REFCLK_DIV 1
 ad_ip_parameter util_ad9371_xcvr CONFIG.CPLL_CFG0 0x67f8

projects/adrv9371x/kcu105/system_top.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -239,7 +239,6 @@ module system_top (
   assign gpio_i[63:60] = gpio_o[63:60];
 
   system_wrapper i_system_wrapper (
-    .dac_fifo_bypass (gpio_o[60]),
     .adc_fir_filter_active (gpio_o[61]),
     .dac_fir_filter_active (gpio_o[62]),
     .c0_ddr4_act_n (ddr4_act_n),

projects/adrv9371x/zc706/Makefile

@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -10,10 +10,12 @@ M_DEPS += ../common/adrv9371x_bd.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/zc706/zc706_system_constr.xdc
 M_DEPS += ../../common/zc706/zc706_system_bd.tcl
-M_DEPS += ../../common/zc706/zc706_plddr3_dacfifo_bd.tcl
+M_DEPS += ../../common/zc706/zc706_plddr3_data_offload_bd.tcl
 M_DEPS += ../../common/zc706/zc706_plddr3_constr.xdc
 M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc
 M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl
+M_DEPS += ../../common/xilinx/data_offload_bd.tcl
+M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
 M_DEPS += ../../../library/util_cdc/sync_bits.v
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 M_DEPS += ../../../library/common/util_pulse_gen.v
@@ -25,17 +27,19 @@ LIB_DEPS += axi_dmac
 LIB_DEPS += axi_hdmi_tx
 LIB_DEPS += axi_spdif_tx
 LIB_DEPS += axi_sysid
+LIB_DEPS += data_offload
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
 LIB_DEPS += jesd204/axi_jesd204_rx
 LIB_DEPS += jesd204/axi_jesd204_tx
 LIB_DEPS += jesd204/jesd204_rx
 LIB_DEPS += jesd204/jesd204_tx
 LIB_DEPS += sysid_rom
+LIB_DEPS += util_do_ram
+LIB_DEPS += util_hbm
 LIB_DEPS += util_pack/util_cpack2
 LIB_DEPS += util_pack/util_upack2
 LIB_DEPS += xilinx/axi_adxcvr
-LIB_DEPS += xilinx/axi_dacfifo
 LIB_DEPS += xilinx/util_adxcvr
 
 include ../../scripts/project-xilinx.mk

projects/adrv9371x/zc706/system_bd.tcl

@@ -1,14 +1,20 @@
 ###############################################################################
-## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2016-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-set dac_fifo_address_width 10
+## Offload attributes
+set dac_offload_type 1                      ; ## PL_DDR
+set dac_offload_size [expr 1024*1024*1024]  ; ## 1 GB
+set plddr_offload_axi_data_width 512
 
 source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
-source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
+source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_data_offload_bd.tcl
+source ../common/adrv9371x_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
+ad_plddr_data_offload_create $dac_offload_name
+
 #system ID
 ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
@@ -23,10 +29,9 @@ S=$ad_project_params(TX_JESD_S)\
 RX_OS:M=$ad_project_params(RX_OS_JESD_M)\
 L=$ad_project_params(RX_OS_JESD_L)\
 S=$ad_project_params(RX_OS_JESD_S)\
-DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
+DAC_OFFLOAD:TYPE=$dac_offload_type\
+SIZE=$dac_offload_size"
 
 sysid_gen_sys_init_file $sys_cstring
 
 ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 200
-
-source ../common/adrv9371x_bd.tcl

projects/adrv9371x/zc706/system_top.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2016-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -246,7 +246,6 @@ module system_top (
   assign gpio_i[63:60] = gpio_o[63:60];
 
   system_wrapper i_system_wrapper (
-    .dac_fifo_bypass (gpio_o[60]),
     .adc_fir_filter_active (gpio_o[61]),
     .dac_fir_filter_active (gpio_o[62]),
     .ddr3_addr (ddr3_addr),

projects/adrv9371x/zcu102/Makefile

@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2025 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -10,9 +10,10 @@ M_DEPS += ../common/adrv9371x_bd.tcl
 M_DEPS += ../../scripts/adi_pd.tcl
 M_DEPS += ../../common/zcu102/zcu102_system_constr.xdc
 M_DEPS += ../../common/zcu102/zcu102_system_bd.tcl
-M_DEPS += ../../common/xilinx/dacfifo_bd.tcl
 M_DEPS += ../../common/xilinx/adi_fir_filter_constr.xdc
 M_DEPS += ../../common/xilinx/adi_fir_filter_bd.tcl
+M_DEPS += ../../common/xilinx/data_offload_bd.tcl
+M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
 M_DEPS += ../../../library/util_cdc/sync_bits.v
 M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl
 M_DEPS += ../../../library/common/util_pulse_gen.v
@@ -22,14 +23,16 @@ M_DEPS += ../../../library/common/ad_bus_mux.v
 LIB_DEPS += axi_clkgen
 LIB_DEPS += axi_dmac
 LIB_DEPS += axi_sysid
+LIB_DEPS += data_offload
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
 LIB_DEPS += jesd204/axi_jesd204_rx
 LIB_DEPS += jesd204/axi_jesd204_tx
 LIB_DEPS += jesd204/jesd204_rx
 LIB_DEPS += jesd204/jesd204_tx
 LIB_DEPS += sysid_rom
-LIB_DEPS += util_dacfifo
+LIB_DEPS += util_do_ram
+LIB_DEPS += util_hbm
 LIB_DEPS += util_pack/util_cpack2
 LIB_DEPS += util_pack/util_upack2
 LIB_DEPS += xilinx/axi_adxcvr

projects/adrv9371x/zcu102/system_bd.tcl

@@ -1,15 +1,15 @@
 ###############################################################################
-## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-## FIFO depth is 16Mb - 1M samples
-set dac_fifo_address_width 17
-
-## NOTE: With this configuration the #36Kb BRAM utilization is at ~51%
+## Offload attributes
+set dac_offload_type 0                   ; ## BRAM
+set dac_offload_size [expr 2*1024*1024]  ; ## 2 MB
+set plddr_offload_axi_data_width 0
 
 source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
-source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
+source ../common/adrv9371x_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
 
 #system ID
@@ -26,16 +26,15 @@ S=$ad_project_params(TX_JESD_S)\
 RX_OS:M=$ad_project_params(RX_OS_JESD_M)\
 L=$ad_project_params(RX_OS_JESD_L)\
 S=$ad_project_params(RX_OS_JESD_S)\
-DAC_FIFO_ADDR_WIDTH=$dac_fifo_address_width"
+DAC_OFFLOAD:TYPE=$dac_offload_type\
+SIZE=$dac_offload_size"
 
 sysid_gen_sys_init_file $sys_cstring
 
 ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
 ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {IOPLL}
 ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 200
 
-source ../common/adrv9371x_bd.tcl
-
 ad_ip_parameter axi_ad9371_tx_xcvr CONFIG.TX_DIFFCTRL 6
 
 ad_ip_parameter util_ad9371_xcvr CONFIG.QPLL_FBDIV 80