library/util_axis_fifo_asym: Fix room and level signals from FIFO ASYM #1920
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Fix a bug where m_axis_valid waits on m_axis_ready to be asserted a few times in order to skip over data for which tkeep was all zeroes. This was a violation of the AXI Streaming protocol. Signed-off-by: Laez Barbosa <[email protected]>
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| .in_clk (m_axis_aclk), | ||
| .in_event (m_axis_ready & m_axis_valid), | ||
| .out_clk (s_axis_aclk), | ||
| .out_event (sdi_output_read_sync)); |
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sdi_output_read_sync I suggest renaming this
Fix tvalid low when tlast is present. Before this commit, util_axis_fifo would suppress all transfers with tkeep=0, even if tlast was asserted. This commit makes it so transfers with tlast asserted are preserved. The AXI-Streaming spec allows us to suppress transfers for which all tkeep bits are 0 (all bytes are null bytes), but only in the case when tlast=0 as well. Transfers where tlast is asserted can't be suppressed even when all bytes are null. Signed-off-by: Laez Barbosa <[email protected]>
On intel projects, the s0,s1 connections were inverted before this commit. s1 is intended for the FIFO mode commands and data, and s0 is intended for the Offload mode ones. This inversion meant that when Offload was enabled, the FIFO commands were sent, and vice-versa. Until recently, before #1502, this was relatively benign, and caused only a priority inversion between the two streams. After #1502, however, it makes the offload enable signal behave wrongly, since it's used for selecting between the s0, s1 interfaces. Signed-off-by: Laez Barbosa <[email protected]>
ROOM and LEVEL signals are incorrect when there is an imbalance between the size of the input and output and TKEEP_EN == 1. This commit fixes this issue by inserting two counters, which are better for timing than performing a sum reduce ROOM and LEVEL of the internal symmetrical FIFOs Signed-off-by: Carlos Souza <[email protected]>
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ROOM and LEVEL signals are incorrect when there is an imbalance between the size of the input and output and TKEEP_EN == 1. This is fixed by inserting two counters, which are better for timing than performing a sum reduce ROOM and LEVEL of the internal symmetrical FIFOs.
This PR has to be merged after #1914
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