Split async and sync ADC into different implementations

boards/same51_curiosity_nano/src/lib.rs

@@ -0,0 +1,194 @@
+#![no_std]
+#![deny(missing_docs)]
+
+//! Board support crate for Adafruit's Feather M4 Express,
+//! an ATSAMD51-based board in Feather form factor.
+
+#[cfg(feature = "rt")]
+pub use cortex_m_rt::entry;
+
+pub use atsamd_hal as hal;
+pub use hal::ehal;
+pub use hal::pac;
+
+use hal::clock::GenericClockController;
+use hal::sercom::{
+    i2c, spi,
+    uart::{self, BaudMode, Oversampling},
+    IoSet1, UndocIoSet1,
+};
+use hal::time::Hertz;
+
+#[cfg(feature = "usb")]
+use hal::usb::usb_device::bus::UsbBusAllocator;
+#[cfg(feature = "usb")]
+pub use hal::usb::UsbBus;
+
+hal::bsp_peripherals!(
+    Sercom1 { SpiSercom }
+    Sercom2 { I2cSercom }
+    Sercom5 { UartSercom }
+);
+
+hal::bsp_pins!(
+    PA02 {
+        /// Analog pin 0.  Can act as a true analog output
+        /// as it has a DAC (which is not currently supported
+        /// by this hal) as well as input.
+        name: a0,
+    }
+    PA05 {
+        /// Analog Pin 1
+        name: a1,
+    }
+    PB08 {
+        /// Analog Pin 2
+        name: a2,
+    }
+    PB09 {
+        /// Analog Pin 3
+        name: a3,
+    }
+    PA04 {
+        /// Analog Pin 4
+        name: a4,
+    }
+    PA06 {
+        /// Analog Pin 5
+        name: a5,
+    }
+    PB01 {
+        /// Analog Vdiv (1/2 resistor divider for monitoring the battery)
+        name: battery,
+    }
+
+    PB17 {
+        /// Pin 0, UART rx
+        name: d0,
+        aliases: {
+            AlternateC: UartRx
+        }
+    }
+    PB16 {
+        /// Pin 1, UART tx
+        name: d1,
+        aliases: {
+            AlternateC: UartTx
+        }
+    }
+    PA14 {
+        /// Pin 4, PWM capable
+        name: d4,
+    }
+    PA16 {
+        /// Pin 5, PWM capable
+        name: d5,
+    }
+    PA18 {
+        /// Pin 6, PWM capable
+        name: d6,
+    }
+    PB03 {
+        /// Neopixel Pin
+        name: neopixel,
+    }
+    PA19 {
+        /// Pin 9, PWM capable.  Also analog input (A7)
+        name: d9,
+    }
+    PA20 {
+        /// Pin 10, PWM capable
+        name: d10,
+    }
+    PA21 {
+        /// Pin 11, PWM capable
+        name: d11,
+    }
+    PA22 {
+        /// Pin 12, PWM capable
+        name: d12,
+    }
+    PA23 {
+        /// Pin 13, which is also attached to the red LED. PWM capable.
+        name: d13,
+        aliases: {
+            PushPullOutput: RedLed,
+            AlternateE: RedLedPwm
+        }
+    }
+    PA12 {
+        /// The I2C data line
+        name: sda,
+        aliases: {
+            AlternateC: Sda
+        }
+    }
+    PA13 {
+        /// The I2C clock line
+        name: scl,
+        aliases: {
+            AlternateC: Scl
+        }
+    }
+    PA17 {
+        /// The SPI SCK
+        name: sck,
+        aliases: {
+            AlternateC: Sclk
+        }
+    }
+    PB23 {
+        /// The SPI MOSI
+        name: mosi,
+        aliases: {
+            AlternateC: Mosi
+        }
+    }
+    PB22 {
+        /// The SPI MISO
+        name: miso,
+        aliases: {
+            AlternateC: Miso
+        }
+    }
+    PA24 {
+        /// The USB D- pad
+        name: usb_dm,
+        aliases: {
+            AlternateH: UsbDm
+        }
+    }
+    PA25 {
+        /// The USB D+ pad
+        name: usb_dp,
+        aliases: {
+            AlternateH: UsbDp
+        }
+    }
+);
+
+/// UART pads for the labelled RX & TX pins
+pub type UartPads = uart::Pads<UartSercom, IoSet1, UartRx, UartTx>;
+
+/// UART device for the labelled RX & TX pins
+pub type Uart = uart::Uart<uart::Config<UartPads>, uart::Duplex>;
+
+/// Convenience for setting up the labelled RX, TX pins to
+/// operate as a UART device running at the specified baud.
+pub fn uart(
+    clocks: &mut GenericClockController,
+    baud: impl Into<Hertz>,
+    sercom: UartSercom,
+    mclk: &mut pac::Mclk,
+    rx: impl Into<UartRx>,
+    tx: impl Into<UartTx>,
+) -> Uart {
+    let gclk0 = clocks.gclk0();
+
+    let clock = &clocks.sercom5_core(&gclk0).unwrap();
+    let baud = baud.into();
+    let pads = uart::Pads::default().rx(rx.into()).tx(tx.into());
+    uart::Config::new(mclk, sercom, pads, clock.freq())
+        .baud(baud, BaudMode::Fractional(Oversampling::Bits16))
+        .enable()
+}

hal/src/peripherals/adc/mod.rs

@@ -183,7 +183,7 @@ impl<I: AdcInstance, Id: ChId> Channel<I, Id, NoneT> {
 
 // These methods are only implemented for a Channel that holds a configured pin
 impl<I: AdcInstance, Id: ChId, P: AdcPin<I, Id>> Channel<I, Id, P> {
-    pub fn read_blocking(&self, adc: &mut Adc<I>) -> u16 {
+    pub fn read_blocking(&self, adc: &mut Adc<I, NoneT>) -> u16 {
         //f(Id::ID as u16);
         adc.read_blocking(Id::ID)
     }
@@ -194,7 +194,10 @@ impl<I: AdcInstance, Id: ChId, P: AdcPin<I, Id>> Channel<I, Id, P> {
     }
 
     #[cfg(feature = "async")]
-    pub async fn read(&self, adc: &mut Adc<I>) -> u16 {
+    pub async fn read<F>(&self, adc: &mut Adc<I, F>) -> u16
+    where
+        F: crate::async_hal::interrupts::Binding<I::Interrupt, async_api::InterruptHandler<I>>,
+    {
         adc.read(Id::ID).await
     }
 
@@ -205,14 +208,12 @@ impl<I: AdcInstance, Id: ChId, P: AdcPin<I, Id>> Channel<I, Id, P> {
 }
 
 /// ADC Instance
-pub struct Adc<I: AdcInstance> {
+pub struct Adc<I: AdcInstance, F = NoneT> {
     adc: I::Instance,
+    _irqs: PhantomData<F>,
 }
 
-pub struct AsyncAdc<A: AdcInstance, I> {
-    inner: A,
-    _irqs: PhantomData<I>,
-}
+pub struct AdcFuture;
 
 impl<I: AdcInstance> Adc<I> {
     /// Construct a new ADC instance
@@ -241,7 +242,10 @@ impl<I: AdcInstance> Adc<I> {
         adc.ctrla().modify(|_, w| w.swrst().set_bit());
         while adc.syncbusy().read().swrst().bit_is_set() {}
         // Calibrate and setup the Vref (This is done once)
-        let mut new_adc = Self { adc };
+        let mut new_adc = Self {
+            adc,
+            _irqs: PhantomData,
+        };
 
         I::calibrate(&new_adc.adc);
         new_adc.configure(settings);
@@ -289,6 +293,29 @@ impl<I: AdcInstance> Adc<I> {
         while self.adc.syncbusy().read().refctrl().bit_is_set() {}
     }
 
+    pub fn read_blocking(&mut self, ch: u8) -> u16 {
+        self.sync();
+        self.mux(ch);
+        self.sync();
+        self.adc.ctrla().modify(|_, w| w.enable().set_bit()); // Enable ADC
+        self.sync();
+        self.adc.swtrig().modify(|_, w| w.start().set_bit()); // Start sample
+        while self.adc.intflag().read().resrdy().bit_is_clear() {}
+        let res = self.adc.result().read().bits();
+        self.adc.ctrla().modify(|_, w| w.enable().clear_bit()); // Stop ADC (No sync required)
+        res
+    }
+
+    pub fn read_ptat_blocking(&mut self) -> u16 {
+        self.read_blocking(0x19)
+    }
+
+    pub fn read_ctat_blocking(&mut self) -> u16 {
+        self.read_blocking(0x1A)
+    }
+}
+
+impl<I: AdcInstance, T> Adc<I, T> {
     #[inline(always)]
     fn sync(&self) {
         // Slightly more performant than checking the individual bits
@@ -372,28 +399,31 @@ impl<I: AdcInstance> Adc<I> {
         while self.adc.syncbusy().read().inputctrl().bit_is_set() {}
     }
 
-    pub fn read_blocking(&mut self, ch: u8) -> u16 {
-        self.sync();
-        self.mux(ch);
-        self.sync();
-        self.adc.ctrla().modify(|_, w| w.enable().set_bit()); // Enable ADC
-        self.sync();
-        self.adc.swtrig().modify(|_, w| w.start().set_bit()); // Start sample
-        while self.adc.intflag().read().resrdy().bit_is_clear() {}
-        let res = self.adc.result().read().bits();
-        self.adc.ctrla().modify(|_, w| w.enable().clear_bit()); // Stop ADC (No sync required)
-        res
-    }
-
     #[cfg(feature = "async")]
-    pub async fn read(&mut self, ch: u8) -> u16 {
+    pub fn into_future<F>(self, _irqs: F) -> Adc<I, F>
+    where
+        F: crate::async_hal::interrupts::Binding<I::Interrupt, async_api::InterruptHandler<I>>,
+    {
         use crate::async_hal::interrupts::InterruptSource;
-        use core::{future::poll_fn, task::Poll};
-        self.disable_interrupts();
         unsafe {
             I::Interrupt::unpend();
             I::Interrupt::enable();
         }
+        Adc {
+            adc: self.adc,
+            _irqs: PhantomData,
+        }
+    }
+}
+
+#[cfg(feature = "async")]
+impl<I: AdcInstance, F> Adc<I, F>
+where
+    F: crate::async_hal::interrupts::Binding<I::Interrupt, async_api::InterruptHandler<I>>,
+{
+    pub async fn read(&mut self, ch: u8) -> u16 {
+        use core::{future::poll_fn, task::Poll};
+        self.disable_interrupts();
         self.sync();
         self.mux(ch);
         self.sync();
@@ -406,7 +436,6 @@ impl<I: AdcInstance> Adc<I> {
                 self.disable_interrupts();
                 return Poll::Ready(self.result());
             }
-
             I::waker().register(cx.waker());
             self.enable_interrupts();
 
@@ -419,19 +448,8 @@ impl<I: AdcInstance> Adc<I> {
         })
         .await;
         self.adc.ctrla().modify(|_, w| w.enable().clear_bit()); // Stop ADC (No sync required)
-        unsafe {
-            I::Interrupt::disable();
-        }
         result
     }
-
-    pub fn read_ptat_blocking(&mut self) -> u16 {
-        self.read_blocking(0x19)
-    }
-
-    pub fn read_ctat_blocking(&mut self) -> u16 {
-        self.read_blocking(0x1A)
-    }
 }
 
 // Here I declare the number of channels for the SAME51 ADC