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perf(agc): handle uniform pattern-fill kernels as clears - #1335
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Recognize the exact typed pattern-fill kernel and route aligned, nonaliased uniform ranges through existing fill/coherence handling. Preserve control and descriptor bounds, partial dispatch counts, queued labels, and shader fallback for other cases. Semantics checked on Radeon RX 6600: native RDNA wave32/wave64 typed R32_UINT loads/stores, execution masks, and descriptor bounds (16 cases). Real PM4 tests cover HLE and shader paths, imports and copies, indirect/partial dispatch and GPU-to-label ordering under Vulkan validation. Graphics and PM4 tests pass; Skyrim Helgen save visually checked. 64 MiB copied-buffer fill median reduced from 67.5 ms to 3.8 ms. Written with AI assistance.
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Rebased on Measured upstream The same fixture submits the real wave32 pattern-fill command stream to each driver. Each size has one warmup and nine measured fills. The uniform pattern alternates each time, so an unchanged result cannot satisfy the next fill. The timer includes submission, wait-idle, and publication to the host buffer; every output word is checked after the timer. Buffers are ordinary unregistered host allocations, with default import settings. Six processes per variant in ABBA × 3 order. Validation is off for timing, and no game or build ran alongside it.
Both variants pass the command-stream correctness cases under RADV core and sync validation. The PR's full pattern-fill suite also passes with default imports, host imports disabled, and HLE disabled. It covers wave32/wave64, indirect and partial dispatches, bounds, nonuniform fallback, and GPU-to-label ordering. Graphics, PM4, and contribution checks pass. This is not title frame time. PS5 hardware and Windows were not tested. AI-assisted. |
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Native Windows run, since no Windows results were posted. Setup: Windows 10 (19045), RTX 3060 Laptop (NVIDIA 616.92), MinGW-w64 GCC 15.2.0 (WinLibs r7), Release. Head
No title was run. 🤖 Addressed by Claude Code |
Adapt the typed pattern-fill kernel from upstream PR boykopovar#1335 and the depth metadata clear path from PR boykopovar#374. Require padded Navi1x metadata coverage and invalidate pending clears on reassociation, retirement, or later tracked stores. Validate typed fills and depth readback on NVIDIA, with focused decoder and kernel regression tests.
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Other open pull requests touch the same code. Merging one will break the other, or both implement the same thing. If this one builds on them, list them in Depends on.
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Checked the exact-kernel match (code words, descriptor strides/formats, thread shape), the uniform/alignment/alias conditions and the dispatch/descriptor clamps against the diff; Note for whoever lands second between this and #2081: both touch |
perf(agc): handle uniform pattern-fill kernels as clears
3 participants
What
Recognize the exact typed pattern-fill kernel. Use the existing clear path when its pattern is uniform and the destination is aligned and does not alias its inputs. Keep shader execution for other cases.
Preserve dispatch bounds, descriptor bounds, queued labels, and partial workgroups. #1201/#1202 change fill scheduling but do not recognize this kernel.
Tested
Fedora 44, Release, RX 6600: graphics and PM4 tests; real dispatch tests with Vulkan validation, HLE on and off, wave32/wave64, indirect and partial dispatches, default import settings and forced copies, and GPU-to-label ordering.
Semantics: 16 native RX 6600 cases checked typed R32_UINT loads/stores, execution masks, and descriptor bounds. PS5 hardware was not tested. Isolated comparison: upstream
e9846679versus the same revision plus this PR. Complete fill-and-publish medians fell from 0.592 → 0.303 ms at 4 KiB, 1.175 → 0.431 ms at 1 MiB, and 92.070 → 7.370 ms at 64 MiB. Six pinned processes per variant in ABBA order; the pattern changes each fill and every output word is checked. These are component timings, not title frame time. Windows was not tested.Checklist
main; no duplicate open PR.