[CouchRiv]

What

Part of #981, a follow-up to #1867. In a shader with IEEE_MODE=1, the cube instructions return a signaling NaN unchanged:

v_cubesc_f32 v10, 0, 0x7fc12345, 0xff812345   hardware 7fc12345, recompiler 7f812345
v_cubetc_f32 v10, 0, 0, 0xff812345            hardware ffc12345, recompiler ff812345
v_cubema_f32 v10, 0xff812345, 0, 0            hardware ffc12345, recompiler ff812345

With IEEE=1 the hardware quiets a signaling NaN result of v_cubesc/cubetc/cubema_f32, and keeps the sign the instruction gives it (cubesc above returns -z). With IEEE=0 the bits pass through. This is the rule #1867 measured for the unary instructions. floatCube picks the NaN operand itself, so these bits never came from the driver: #1867 recorded v_cubema as "left to the driver", but the code always returned the signaling NaN as it was. floatCube now passes a NaN result through quietNan32. IEEE=0, shaders without a known float mode and v_cubeid_f32 behave as before. With DX10_CLAMP=1 a clamped NaN still becomes 0; with DX10_CLAMP=0 it keeps its sign and payload and is quieted only with IEEE=1 (row 2 v_cubema_f32 ... clamp: 7f800001 at IEEE=0, 7fc00001 at IEEE=1 on gfx1036).

Which title needs it

No known title needs it yet. It extends the rule #1867 measured to three more instructions, and it only changes shaders running with IEEE=1, which titles we know do not use (they use 0xc0, IEEE=0).

Tested

CachyOS Linux, GCC 16.2, RTX 4070 Ti (NVIDIA 615.71) and Radeon 610M (RADV, Mesa 26.2.4). Measured on RDNA2 (gfx1036) with the HW oracle.

• agc_driver_vop3_cube_clamp now also runs at IEEE=0 and IEEE=1. Its 16 forms × 32 rows were captured on hardware in both modes. The IEEE=0 capture equals the existing table. At IEEE=1, 12 of the 512 cells differ, all signaling NaN results of sc/tc/ma, with and without source modifiers.
• Without the fix the test fails on both drivers: lane 2 IEEE=1 v_cubema_f32 v13, v4, v5, v6 is 0x7f800001, expected 0x7fc00001.
• A differential run of 2,744 rows per instruction in 4 float modes: 114 (cubesc), 278 (cubetc) and 196 (cubema) rows differed with IEEE=1 before, 0 after, on both drivers. v_cubeid_f32 still matches.
• Full Release ctest 498/498 on NVIDIA and on RADV; check_conventions.py and git diff --check pass.
• Not tested: a title, since none is known to run with IEEE=1.

Checklist

• Based on current main; no other open PR implements the same functions
• One topic per PR; follow-ups go in a new PR
• No comments in code except technical debt
• Unimplemented paths throw (NotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt
• No notes, investigation .md files or images added to the repository (attach them to this PR)
• New third-party code is a submodule built from source
• Generic behaviour, not specific to one title
• Depends on: none (fix(shader): quiet signaling NaNs only in IEEE mode #1867 merged). fix(shader): quiet signaling NaN halves in v_pack_b32_f16 in IEEE mode #2042 (mine, v_pack_b32_f16) edits the same TechnicalDebt sentence; I'll rebase whichever lands second
• AI-assisted: yes

🤖 Generated with Claude Code

[popcoder565]

Native Windows run, since no Windows results were posted. Setup: Windows 10 (19045), RTX 3060 Laptop (NVIDIA 616.92), MinGW-w64 GCC 15.2.0 (WinLibs r7), Release. Head f3660a0c, merged onto main d70b899 in one build with 33 other AGC/shader PRs that had no Windows run.

• This PR's tests pass: agc_driver_vop3_cube_clamp. None of them reported skipping a case.
• Full ctest in that build: 514 of 515. The one failure is fix(agc): defer a shader whose code does not decode instead of aborting the title #2257's new test, which is registered without the Windows PATH setup.

No title was run.

🤖 Addressed by Claude Code

[adriadam10]

Rebased on current main (only conflict: the Signaling NaN inputs line in TechnicalDebt.md, now keeps main's text plus the cube sentence). The red linux/windows jobs failed building agc_shader_fusion_tests (spirv/unified1/spirv.hpp missing), which this PR doesn't touch.

Checked on the rebased head: full build and ctest 633/633; agc_driver_vop3_cube_clamp fails without the change; the HW-oracle rows on RDNA2 (gfx1035) match bit for bit in both IEEE modes. Merging once the rebase is pushed.

[adriadam10]

Rebased on current main (conflict in the Signaling NaN inputs line of TechnicalDebt.md after #2042's sentence: kept main's text plus the cube sentence). Added one commit: that line still listed v_cubema among the instructions whose NaN bits are left to the driver, which this PR makes false; removed it.

Checked on the rebased head: scoped build and ctest 324/324 (libSceAgc, libSceAgcDriver); agc_driver_vop3_cube_clamp fails without the change; HW-oracle rows on RDNA2 (gfx1035) match bit for bit in both IEEE modes. Windows run by @popcoder565 passes too. Merging once CI is green.