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fix(shader): read GLC/DLC BDA dwords with device-scope atomic loads - #2259
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Tested exact PR head Environment: Windows 11 Pro 10.0.26200, Ryzen 7 7700X, RX 7900 XT (RDNA 3, Vulkan device 0x744c), AMD driver 32.0.31041.1004, Vulkan 1.4.349. WinLibs GCC 15.2.0 UCRT/POSIX/SEH r7, Release, BUILD_TESTING=ON, SPIRV-Tools OFF. ANYPS5_GPU=7900 XT and ANYPS5_REQUIRE_VULKAN=1.
No title test or native-instruction hardware oracle was performed. No modifications to the PR implementation are proposed. |
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Reviewed the diff: the atomic path is only taken for mapped, 4-byte-aligned addresses ( What we can't confirm here: the test also passes without the change on RADV/lavapipe (and on an RX 7900 XT per @joelfernandes23), so it only fails on NVIDIA, which we can't run. @oneandonlydean could you run @TheAggie: this conflicts with #2349 in |
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Additional platform validation on standalone PR head Linux: passed — Arch Linux in WSL2 (kernel 6.6.87.2), GCC 16.2.1 20260810; CMake 4.3.1 / Ninja. Release / Tests: Reproduce after building the test targets: Vulkan: Mesa lavapipe 26.2.4 software Vulkan; no native Linux GPU/retail-title validation. |
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Independent validation on real hardware I built and ran the PR head
Result with the fix (PR head):
Rigor check (is the test real, or a pass-through?): I reverted only
Restoring the fix puts it back to PASS. So this is a genuine regression test: it fails on base NVIDIA and the atomic-load change is exactly what turns it green — which matches the author's reported "result 3 → result 2" on NVIDIA. Bottom line: On my 5090/4090/iGPU the PR is green, the new test is a real (non-pass-through) regression test, and it additionally passes on an AMD iGPU beyond what was reported. I did not test Linux/macOS or the 5070 Ti, and I didn't evaluate the noted textual conflict with #1267 (rebase is the author's call). Written with AI assistance. |
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Same as fma-rc's note above, still the case on current AI-assisted (Claude Code). |
Coherent (GLC/DLC) global loads were emitted as Volatile loads through physical pointers. Volatile does not make another workgroup's stores visible within the same dispatch, so a workgroup spinning on a flag written by another one (decoupled look-back scans, as in RADV's acceleration-structure build) never saw it on NVIDIA. Aligned coherent dword reads now use OpAtomicLoad at device scope; the byte path keeps the old reads for unaligned addresses. AI-assisted (Claude Code). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Thanks @fma-rc and @Silverash-i8, fixed. The branch is rebased onto On Windows 11 / RTX 5070 Ti it builds again, and AI-assisted (Claude Code). |
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Checked the diff (atomic path only for mapped, 4-byte-aligned addresses; byte path and non-coherent loads unchanged; phi/merge structure correct). Built merged onto main: |
What
A GLC/DLC global load is translated as a
Volatileload through a physical-storage pointer. Under the GLSL450 memory model,Volatiledoesn't make another workgroup's stores visible within the same dispatch. On NVIDIA, a workgroup that spins on a flag written by another workgroup never sees the store.This is the pattern of decoupled look-back prefix scans. RADV's acceleration-structure build uses it (the radix sort), and vkQuake (PPSA99010) triggers that build with
r_rtshadows. Under AnyPS5 the scan spins until the GPU is lost (VK_ERROR_DEVICE_LOST), or spins silently.When the non-faulting BDA probe gives a coherent dword read a non-null, 4-byte-aligned physical address,
SpirvBdaRead.cppnow emitsOpAtomicLoadatScopeDevicewith relaxed semantics instead ofOpLoad ... Volatile. That covers the wide path inEmitBdaDwordReadsand the coherent single-dword helper inDefineBdaDwordReadFunctions. Unaligned addresses, unmapped addresses and reads that span two BDA ranges still take the existing byte path, which reports faults exactly as before. With byte reads forced (no probe), nothing changes. Non-coherent loads are unchanged.Tests:
tests/execution/CrossWorkgroupFlag.cpp: 25 hand-assembled GFX10 words, two workgroups. Workgroup 0 stores a flag withglobal_store_dword glc. Workgroup 1 spins onglobal_load_dword glc dlcand writes 2 if it sees the flag, or 3 after a 1M-iteration bailout, so a failure can't hang the GPU. It runs as wave64 and wave32. A control run with the flag preset by the CPU checks the harness itself.This conflicts textually with #1267, which reworks the same read sites; I'll rebase onto whichever lands first.
Tested
Windows 11 Pro (26200), MinGW-w64 GCC 15.2.0 (WinLibs r7), Release, NVIDIA GeForce RTX 5070 Ti (driver 610.88).
guest_sce_nettimed out (it times out locally on unrelated branches too, likely my network filtering). It was run from the generatedCTestTestfile.cmakecommands because antivirus blocksctest.exeon this machine.tools/check_conventions.py --base origin/mainpasses.CrossWorkgroupFlagfails on this NVIDIA GPU without the change and passes with it; lavapipe passes either way.mainplus my open RADV PRs and local stubs): the GPU hang during RADV's BVH build went away. The build's output is still wrong for a separate reason I haven't found yet, sor_rtshadowsdoesn't work yet.Not tested on Linux or macOS.
Checklist
main; no other open PR implements the same functionsNotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt.mdfiles or images added to the repository (attach them to this PR)🤖 Generated with Claude Code