[SleglJan]

What

Two TechnicalDebt entries said what the recompiler assumes without a hardware measurement. Measured on RDNA2 (gfx1036, Ryzen 7950X3D iGPU) with tools/hw-oracle (Linux, CachyOS kernel 7.2.9, hsa-rocr 7.2.4, clang 23.1.1 as the assembler, tools at main d70b899, mode IEEE 0, f32 denormals flushed, f16/f64 kept, DX10_CLAMP 1, RNE), in wave32 and wave64, and recorded in the entries:

• s_call_b64 (SIMM16 = 3): the link pair receives PC + 4 and the branch goes to PC + 4 + signext(SIMM16) * 4; s_setpc_b64 of the link returns to the instruction after the call (a counter shows the callee, +1, and the return path, +2, each ran once). The entry's "native RDNA2 ... execution" becomes measured; execution on the PS5 (gfx1013) and title compatibility stay unverified.
• s_swappc_b64 with SDST 125 (the null register): the hardware branches to the source pair (the instruction at the skipped address is not executed) and leaves a marker SGPR pair untouched; with an SGPR destination the link is PC + 4. So the existing decode as s_setpc_b64 matches the hardware.
  The s_memtime measurements from the same run are posted on fix(agc): detect AMD proprietary narrow clock #1632, which rewrites that entry.

No code changes. Bodies, rows, outputs and the script: https://github.com/SleglJan/AnyPS5/tree/audit/oracle-2026-10-08/oracle-audit/scalar-misc.

Tested

tools/check_conventions.py --base upstream/main passes; the entries are documentation only.

Overlap: #2302 (open) edits the same s_swappc_b64 entry, and #2161 and #2178 add entries next to the s_call_b64 one; none of them shares code with this PR or is built on by it, so whichever merges second needs a one-line rebase.

Checklist

• Based on current main; no other open PR implements the same functions
• One topic per PR; follow-ups go in a new PR
• No comments in code except technical debt
• Unimplemented paths throw (NotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt
• No notes, investigation .md files or images added to the repository (attach them to this PR)
• New third-party code is a submodule built from source
• Generic behaviour, not specific to one title
• Depends on: none
• AI-assisted: yes (Claude Code)

🤖 Generated with Claude Code

[SleglJan]

The overlap is TechnicalDebt only: #2302 rewrites the s_swappc_b64 entry this PR extends by one sentence, and #2161 and #2178 add entries next to the s_call_b64 one. No shared code and no dependency; whichever merges second needs a one-line rebase, noted in the description.

AI-assisted: yes (Claude Code).

[adriadam10]

Reproduced both measurements on gfx1035 with tools/hw-oracle, wave32 and wave64: s_call_b64 SIMM16 = 3 gives link = PC + 4, the callee and the return path each run once, and the skipped instruction doesn't run; s_swappc_b64 with SDST 125 branches to the source pair, skips the instruction in between and leaves M0 and a marker SGPR pair untouched; with an SGPR destination the link is PC + 4. Rebased onto main (adjacency conflict with the #2178 entry, both lines kept); merging.