[oneandonlydean]

What

#1268 reads lanes 31 and 63 of a wave64 DPP row scan as subgroup reductions, and returns the identity for lane 63 on a 32-lane host subgroup. It does this only when it can prove that the scan's keys are the identity outside the entry EXEC (EntryLaneWalk::ZeroBit). When the key select's mask is written inside a divergent branch, the mask reaches the select as a SelectU1 of bool Phis, and the proof gave up. The read then threw at preparation:

ShaderRecompiler::Recompile: SPIR-V emission failed: hash=0x21476784128 stage=2 opcode=ReadLane reason=v_readlane_b32 of lane 63 is outside the 32-lane host subgroup that runs this wave64 program at one lane per invocation

ZeroBit now also accepts:

• a constant false;
• a SelectU1 whose two values both prove it;
• a bool Phi whose inputs all prove it, with the same cycle handling Word uses for mask Phis.

No new semantics: the emitted reduction is #1268's.

Before #639 such a shader failed only when the draw ran. Preparation now compiles it at the ABI helper, so the throw stops the title there.

Touches core/shader/recompiler/SpirvBackend/src/SpirvAlu/SpirvAluEmitterMath.cpp.

Tested

• Linux (CachyOS, GCC 16.2, RTX 4090, NVIDIA 610.57), on main a8b032b: ctest 495/495. tools/check_conventions.py passes.
• agc_shader_memory, verifyHalfWaveReduction: the UMin scan with its key mask written inside an s_and_saveexec_b64 / s_cbranch_execz branch reads lane 31 as a subgroup UMin on 32 lanes. On main it throws the lane 63 line above. The existing refusals (entry-EXEC keys, WQM mask, bound_ctrl, wrong permlane or join op) still throw.
• A heavier title: a wave64 pixel shader with an OR reduction of this shape stopped launch with the line above. With this, registration goes on.

Checklist

• Based on current main; no other open PR implements the same functions
• One topic per PR; follow-ups go in a new PR
• No comments in code except technical debt
• Unimplemented paths throw (NotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt
• No notes, investigation .md files or images added to the repository (attach them to this PR)
• New third-party code is a submodule built from source
• Generic behaviour, not specific to one title
• Depends on: none
• AI-assisted: yes

[popcoder565]

Native Windows run, since no Windows results were posted. Setup: Windows 10 (19045), RTX 3060 Laptop (NVIDIA 616.92), MinGW-w64 GCC 15.2.0 (WinLibs r7), Release. Head 8a581853, merged onto main 09a3462 in one build with #2473, which current main needs to build on Windows, and 3 other new PRs.

• This PR's tests pass: agc_shader_memory and agc_shader_bindless.
• Full ctest in that build: 546 of 546.

No title was run.

🤖 Addressed by Claude Code

[Kikoarl]

Tested on Linux (CachyOS x86_64, Intel RPL-S iGPU / Mesa 26.3.0-devel / Vulkan 1.4.363, GCC 16.2.1) at 8a581853:

• Build: Built cleanly in RAM (/tmp/anyps5_build) with zero warnings/errors.
• Conventions: python3 tools/check_conventions.py --base origin/main --head HEAD -> PASS (0 errors).
• Verification: Verified bit proof logic for half-wave reduction keys in SpirvAluEmitterMath.cpp. Correctly proves reduction validity across selected/merged lane bit patterns.

LGTM!