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ci: merge train for 8 reviewed PRs (CI batch, do not merge) - #2555
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oneandonlydean wants to merge 19 commits into
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oneandonlydean wants to merge 19 commits into
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Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…re never set PPSA22520 routes its title music through port matrix 0 without setting the matrix levels, so the music rendered silent. A matrix without levels now mixes like a port without a matrix, source channel n to destination channel n. The console's initial levels are unknown; the assumption is recorded in TechnicalDebt. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…ult channel map A port without a matrix sent source channel n to destination channel n, so a mono voice reached only the left channel of a stereo mix. The PS4 firmware 11.00 libSceNgs2.sprx mixes such ports, and ports whose matrix levels were never set, through a fixed channel map instead: mono reaches both stereo channels at -3 dB and the centre of 5.1 and 7.1, stereo folds to mono at -3 dB per side, and wider sources fold down with 0.5 and -3 dB gains. The map was measured for every source width into 1, 2, 6 and 8 channels. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…ault map render Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Untracked host imports may retain pending image results on the GPU after an unchanged refresh. Assert that behavior and verify that an explicit FlushPending makes the results visible in guest memory, while watched memory still checks refresh write-back. Fixes boykopovar#2155
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
A wave64 vertex program reduces a float key across the wave with the same shape as the integer half-wave reductions: keys selected under the all-lanes EXEC with -inf (v_max_f32) or +inf (v_min_f32) outside the entry EXEC, four DPP row_shr steps, v_permlanex16_b32, then v_readlane_b32 of lanes 31 and 63, combined by one more v_max_f32. On a 32-lane host subgroup the read of lane 63 threw that it is outside the subgroup. The matcher now also accepts FPMax32 and FPMin32 steps, with their BitCasts and the f32 denormal flush the float mode may add around operands and results; the flush leaves the -inf and +inf keys unchanged. When the entry EXEC proves that lanes 32-63 hold the constant key, every step there combines that constant with itself. The existing v_max_f32/v_min_f32 lowering returns the operand unchanged for equal operands (NaN included), so lane 63 is exactly that constant, and the read returns it. No subgroup float reduction is emitted. Lane 31, the lanes on a 64-lane subgroup, and the combining v_max_f32 keep their existing lowering. So NaN and signed-zero results are the ones the shader computes today.
A CMASK that was neither all fast-cleared nor all expanded threw, so a title that fast clears a target and then draws over part of it before the eliminate could not run past it. The CMASK is now decoded tile by tile: one nibble per 8x8 tile in 1024x512 metablocks of 4 KiB, addressed with the pipe-aligned SW_64KB_Z_X CMASK equation for 16 pipes (addrlib GFX10_CMASK_SW_PATTERN, Gfx10Lib::HwlComputeCmaskAddrFromCoord). Code 0 stores CB_COLOR_CLEAR_WORD into the tile's texels, 0xF keeps them; any other code, a cleared tile of a DCC target and any other CMASK swizzle mode throw. Edge tiles are included and the CMASK is then stored as expanded. For a resident target whose CMASK is host-imported the clear is a compute pass recorded in stream order: it reads the nibbles from the import, stores the clear into the cleared tiles through a UINT view of the image and fills the CMASK expanded, so nothing waits for pending GPU writes of the CMASK. Invalid codes it reads set a bit that the next materialization throws on. Otherwise the CPU reads the CMASK and stores the cleared tiles into guest memory, or fills the resident image when every tile is cleared. A CMASK nothing has stored over since it was expanded is skipped. The decode requires CB_COLOR_ATTRIB3 FMASK_SW_MODE SW_64KB_Z_X with CMASK_PIPE_ALIGNED, a 4 KiB aligned writable CMASK and texels of at most 64 bits, and CMASK_BASE_EXT is part of the draw key. Tests: CMASK sizes and nibble addresses against addrlib; decode rejections and draw key coverage; CPU eliminate of full, partial, out-of-range-nibble and DCC decompress cases and invalid codes. The new agc_driver_cmask_fast_clear GPU test draws over fast-cleared and partly fast-cleared linear and SW_64KB_R_X targets, eliminates partial, edge and checkerboard CMASKs through the compute pass and checks that an invalid code it reads throws.
This was referenced Oct 10, 2026
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Other open pull requests touch the same code. Merging one will break the other, or both implement the same thing. If this one builds on them, list them in Depends on.
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This was referenced Oct 10, 2026
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Train build 38027196536 was green; the listed pull requests were merged individually. Closing. |
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CI batch for the pull requests below, merged onto main b667d1e in this order. Do not merge this PR. It exists only so one full build tests them together; each PR is merged on its own after this build is green, and this PR is then closed.