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Rebase the graphics proposal onto upstream b42ef24 without carrying the historical macOS merge chain. Includes the compiler/runtime prerequisite from PR boykopovar#1835 and the still-required macOS foundation from mugurc/macos-port at 21930ce; those platform changes remain until their upstream PRs land. Preserve upstream starting-quad folding and the qualified vertex lane rule. Keep x87-dependent Math.cpp outside the optional ARM64 graphics closure rather than weakening its ABI assertion.
Rebase the graphics proposal onto upstream b42ef24 without carrying the historical macOS merge chain. Includes the compiler/runtime prerequisite from PR boykopovar#1835 and the still-required macOS foundation from mugurc/macos-port at 21930ce; those platform changes remain until their upstream PRs land. Preserve upstream starting-quad folding and the qualified vertex lane rule. Keep x87-dependent Math.cpp outside the optional ARM64 graphics closure rather than weakening its ABI assertion.
This was referenced Oct 15, 2026
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What
Extend the whole-image AOT path from #4599 to the bounded C++ profile exercised by yaml-cpp: LSDA-derived landing-pad/resume entries, guest nonlocal return propagation, variant-II static TLS, raw x87 80-bit moves, aligned locked RMW/CAS, and the required Darwin glibc provider boundaries.
Guest exception and unwind routines linked into the input are themselves converted to ARM64. This is not a new native LLVM exception personality: generated functions retain guest registers and a separate guest stack, with checked dispatch to converted entries. No x86 decoder, interpreter, JIT or runtime compiler is linked into the result. The signature-qualified AOT path remains separate.
The takeover review added two corrections beyond the recovered checkpoint: implicit locked XCHG now verifies alignment before emitting aligned LLVM atomics; CMPXCHG without LOCK performs an unaligned volatile read and unconditional write cycle rather than claiming aligned atomic access. A specification-based test checks all six arithmetic flags and partial register/memory results, including success/failure at 8/16/32/64 bits. This complements the Rosetta instruction lab, which checks only ZF for CMPXCHG because its observed other flags disagree with the subtraction semantics in Intel SDM and QEMU.
The provider increment covers the tested C locale, wide-character, pthread synchronization and image-query interfaces. General thread creation/cancellation, ordinary shared-memory x86 ordering, dynamic modules, arbitrary PS5 startup, AVX and general x87 arithmetic remain outside this profile. Naturally unaligned locked accesses reject explicitly; this does not implement every x86 locked-access case.
Tested
Apple Silicon/macOS, local final stack aligned with main
2f4cc8983: 588 compiler/relinker/runtime checks passed, including the restored Rosetta lab after a machine restart and the new independent CAS regression. The pre-correction alignment regression failed for implicit XCHG; it passes with the fix.The source-built, sectionless yaml-cpp 0.9.0 parser matched 147/147 file/stdin/error cases against the independently source-compiled ARM64 reference. The source-built, sectionless zstd 1.5.7 CLI still matched 61/61 cases, including independent decoding of compressed output. These are source-equivalent comparisons, not execution of the same ELF on Linux or PS5. Existing exception-control-flow examples and provider/TLS tests passed.
Shared-platform regression: rebuilt AOT/reference graphics completed 600 flips each, teardown and eight exact RGB frame comparisons; the typed modular consumer and controller acceptance passed. Test registration and conventions were checked on the final changes. Hosted checks on the new head are pending; full Linux/Windows builds require maintainer dispatch.
Reproduction of the standalone lowering and the instruction/provider tests is documented in BUILD.md. The complete external-program receipts remain outside the repository. No game compatibility, controlled speedup or general concurrency claim.
Checklist