[adriadam10]

What

This implements the three MIMG float atomics, which threw as unknown opcodes. The ISA sweep found them.

Opcode	Semantics (measured on an RDNA2 GPU)
image_atomic_fcmpswap (0x1d)	texel = (texel == cmp) ? src : texel, compared as floats: −0 equals +0, NaN equals nothing. vdata[0] = src, vdata[1] = cmp, dmask must be 0x3 like image_atomic_cmpswap
image_atomic_fmin (0x1e) / image_atomic_fmax (0x1f)	IEEE minNum/maxNum: −0 < +0. A signalling NaN operand gives that NaN quieted (src first). A quiet NaN loses to a number. Two quiet NaNs give src

These are the same rules the float buffer atomics follow in #332. On the hardware the image forms gave the same results as the buffer forms (800/800 rows), and the same results on a 32_UINT and a 32_FLOAT T#. Without glc the data VGPR is left untouched, as for the other image atomics.

Implementation:

• Decoder, IR opcode and dispatch entries next to the integer image atomics.
• The emitter runs AtomicUpdate's compare-exchange loop on the existing u32 texel pointer, as image_atomic_inc/dec already do. The value is computed on the raw bits through feat(shader): implement the float and 64-bit inc/dec buffer atomics #332's AtomicFloatBits, which is reached through two helpers, AtomicFloatMinMax and AtomicFloatCompareSwap. So the driver's float controls (denormals, NaN payloads) don't matter, and no Vulkan float-atomic feature is needed.
• Image atomics are still only accepted on 32_UINT textures (ResourceMaterializer, "atomic image descriptor uses an unsupported format"). A float-format texture keeps throwing there. Accepting one needs a uint view of a float texture in the driver, which belongs in a separate PR.

Tested

Arch Linux, RDNA2 iGPU (Radeon 660M), RADV and lavapipe. No title.

New execution test agc_driver_image_atomics_float_tests (ImageAtomicsFloat.cpp):

• 800 rows, measured on hardware: every pair of 20 special values (±0, ±1, ±inf, qNaN/sNaN with payloads, ±denormal min/max, ±π, max finite, min normal), once with cmp = src and once with cmp = old.
• Each row checks the returned value and the resulting texel for fmin, fmax and fcmpswap with glc, and fmin without glc. Everything is compared bit for bit. The emitted code only uses integer ops on the bits, so NVIDIA's NaN canonicalisation doesn't apply.
• It runs as wave32, as wave64 and as wave64 split into two 32-wide halves (ComputeTarget(32)).
• 0 s cold on CI's lavapipe (Mesa 25.2.8).

The test fails without the change in each of these cases (each checked separately):

• fmin and fmax swapped
• a signed-integer min/max instead of the float rule
• fcmpswap comparing bits instead of floats
• src and cmp swapped
• the comparator not read

Release build: full ctest passes except agc_driver_pixel_helper_lanes, which also fails on main on local RADV.

Checklist

• Based on current main; no other open PR implements the same functions
• One topic per PR; follow-ups go in a new PR
• No comments in code except technical debt
• Unimplemented paths throw (NotImplemented_nid_no_patch); silent stubs are listed in TechnicalDebt
• No notes, investigation .md files or images added to the repository (attach them to this PR)
• New third-party code is a submodule built from source
• Generic behaviour, not specific to one title
• Depends on: feat(shader): implement the float and 64-bit inc/dec buffer atomics #332 (on feat(shader): implement buffer_atomic_inc/dec and the 64-bit integer buffer atomics #321), whose two commits are included here. Only the last commit is new.
• AI-assisted: yes

[github-actions]

Progress report (d7f0c49 → d1f7710)

📈 GPU shader instructions: 81.99% (+1.72%, +20 implemented instructions)

✅ 20 implemented

Encoding	Name
MIMG	IMAGE_ATOMIC_FCMPSWAP
MIMG	IMAGE_ATOMIC_FMAX
MIMG	IMAGE_ATOMIC_FMIN
MUBUF	BUFFER_ATOMIC_ADD_X2
MUBUF	BUFFER_ATOMIC_AND_X2
MUBUF	BUFFER_ATOMIC_CMPSWAP_X2
MUBUF	BUFFER_ATOMIC_DEC
MUBUF	BUFFER_ATOMIC_DEC_X2
MUBUF	BUFFER_ATOMIC_FCMPSWAP
MUBUF	BUFFER_ATOMIC_FCMPSWAP_X2
MUBUF	BUFFER_ATOMIC_FMAX_X2
MUBUF	BUFFER_ATOMIC_FMIN_X2
MUBUF	BUFFER_ATOMIC_INC
MUBUF	BUFFER_ATOMIC_INC_X2
MUBUF	BUFFER_ATOMIC_SMAX_X2
MUBUF	BUFFER_ATOMIC_SMIN_X2
MUBUF	BUFFER_ATOMIC_SUB_X2
MUBUF	BUFFER_ATOMIC_UMAX_X2
MUBUF	BUFFER_ATOMIC_UMIN_X2
MUBUF	BUFFER_ATOMIC_XOR_X2

[oneandonlydean]

Thanks. I checked the encodings with llvm-mc for gfx1013: image_atomic_fcmpswap, image_atomic_fmin and image_atomic_fmax are MIMG opcodes 0x1d, 0x1e and 0x1f, and the RDNA2 ISA guide gives the same semantics you measured (fcmpswap stores src when tmp == cmp as a float compare, with DATA[0] = src and DATA[1] = cmp, so dmask 0x3 like cmpswap). The emitter reuses #332's AtomicFloatBits through the existing AtomicUpdate loop on the u32 texel pointer, the same way image inc/dec already work, so the result never depends on the driver's float controls. equal treats -0 and +0 as equal and a NaN as equal to nothing, and minMax is the rule I already checked on #332.

The first two commits are patch-identical to #321 and #332, so this lands after them. Image atomics are still only accepted on 32_UINT views, and float-format textures keep throwing in the materializer, which is the right place to stop for now.

agc_driver_image_atomics_float passes on my NVIDIA machine on current main (with #321 and #332), and fails on main's code.

One note for the merge order: #506 also edits SpirvMemoryInstructions.cpp next to the same helpers and conflicts textually with this one, so whichever lands second needs a small rebase.

This only adds encodings that main refused, so it's ready to merge from my side once #321 and #332 are in.