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fix(relinker): lower ANDN in Rosetta conversion - #5784
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Other open pull requests touch the same code. Merging one will break the other, or both implement the same thing. If this one builds on them, list them in Depends on.
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Measured on a different Apple silicon machine: M2 Max, macOS 27.2 (26B5091g). Relinker-only build of this branch (
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Verified on macOS 27.0.1 (26A434), Apple M4, x86-64 under Rosetta 2, Apple clang 21: the relinker-only build passes |
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Independent Linux x86-64 execution coverage at exact head Ubuntu 24.04, Ryzen 9 9950X, GCC 13.3, Ninja Release,
This fills Linux host execution/conversion coverage. No new title run or Rosetta execution claim; the reported title's SIGILL is not reproduced on this AMD host. |
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M4 Pro, macOS 27.0.1 (26A434), Apple clang 21, PR head 9acd5dc, relinker-only build like the M2 Max run, plain ANDN doesnt fault here. a small x86_64 program that runs the 32 and 64-bit register forms gets the right result under Rosetta, no SIGILL (memory forms not tested) AI-assisted (Claude Code), I ran all of the above on my machine |
agc_pending_key_stores cleared only the first 256 bytes of its 64 KiB block and then asked for the keys of 512 bytes. The other 256 were whatever the heap held: when they were not all equal the range read as mixed (correctly) and the check that it is unknown failed, so the test passed or failed with the allocator's state (main builds after #5784). Co-Authored-By: Claude <noreply@anthropic.com>
What
Balatro (PPSA21402, discussion #1142) stops in its bundled libc initializer on
andnq %rsi, %rcx, %raxunder Rosetta on an Apple M1 running macOS 15.3.1. A standalone x86-64 ANDN program reproduces SIGILL without game files.--to-rosettapreviously left ANDN unchanged.Lower 32- and 64-bit ANDN register and memory forms to scalar NOT/AND sequences. Preserve source and scratch registers, the caller's red zone, stack-relative addressing, RIP-relative operands, and the defined status flags. Plain conversion and
--to-intelkeep ANDN unchanged. Invalid VEX forms and a stack displacement that cannot accommodate the spill frame fail explicitly.Semantics follow the ANDN entry in Intel SDM volume 2A. The documentation now distinguishes the earlier M5 Max observations from the instruction support observed on this M1.
Tested
shlxq %rax, %rdx, %r8, another unsupported instruction. This PR does not establish playability or FPS.macos-portatb7eb6b6b515c6163b6a0a6dd09b630a0414a0149, with the local Apple SDK input-number parsing build fix. The relinker is built from this upstream-based branch.git diff --checkpass. Linux/Windows execution has not been run locally; their existing CI can exercise the portable conversion checks, and Linux x86-64 also executes the lowering test.Checklist
main; no other open PR implements the same functions