Repository navigation
docs(debt): cite radeonsi for the front half's OC_LDS_EN in shader fusion - #7815
Merged
Merged
Conversation
Collaborator
|
Checked the two cited radeonsi lines at Mesa 45ea3ed8 (L631, L1144): both set OC_LDS_EN from the ES stage being tessellation evaluation, as described; docs-only, Conventions green; merged. |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
What
The GS shader-half fusion entry in
docs/dev/debt/libSceAgc.mdsays keepingSPI_SHADER_PGM_RSRC2_GS.OC_LDS_ENfrom either half (#6653) "is inferred from retaining both halves' requirements". There is a source for it: Mesa's radeonsi builds the same merged ES+GS program and sets the bit from the ES stage alone, in bothsi_shader_gs_legacyandgfx10_shader_ngg:So the bit is the front (ES) half's: it is set when that half is a tessellation evaluation shader. The entry now cites those two lines (permalinks at Mesa 45ea3ed8) instead of calling the rule inferred, and keeps the note that console fusion output has not been measured.
Tested
main46f2762 with a temporary print inMergeRsrc2, not part of this PR): 6 distinct pairs, every front half the ES-stage half and every back half the GS half. Four front halves setOC_LDS_EN(RSRC20x00070004), two do not (0x00030018), and no back half sets it. The title also creates tessellation-plus-geometry pipelines (VGT_SHADER_STAGES_EN=0x2135, whose ES stage is the domain shader), the case where radeonsi sets the bit.tools/check_conventions.py --base origin/mainpasses.Checklist
main; no other open PR implements the same functionsNotImplemented_nid_no_patch); silent stubs are listed under Silent stubs in their library's technical debt file.mdfiles or images added to the repository (attach them to this PR)