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docs(relinker): record Rosetta instruction support on an M2 with macOS 14.8.9 - #7953
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Other open pull requests touch the same code. Merging one will break the other, or both implement the same thing. If this one builds on them, list them in Depends on.
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jotitadev
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Data point from the same chip generation on a newer macOS. It suggests the M2 difference follows the macOS version, as the existing entry already says for the M1.
Apple M2 Max, macOS 27.2 (26B5112a). Same method as #7185 and this PR: one forked x86-64 process per instruction, built with clang -arch x86_64 (Apple clang 21.0.0), sysctl.proc_translated = 1, and results compared with expected values. Three runs gave identical results.
cpuid leaf1 ecx=0298220f edx=0f8b8b15
leaf7 ebx=00000000 ecx=00000000
leaf80000001 ecx=00000001 edx=28100800
ANDN BEXTR BLSI BLSMSK BLSR BZHI MULX PDEP PEXT RORX SARX SHLX SHRX execute, results match
TZCNT LZCNT POPCNT MOVBE (TZCNT(0) = 64) execute, results match
AVX AVX2 FMA F16C RDRAND execute, results match
CLFLUSHOPT PREFETCHW execute
RDTSCP executes, ECX = 0xaaaaaaab
RDSEED RDPID CLWB ADCX ADOX SIGILL
- The CPUID leaves are bit-for-bit the ones in your M2 / macOS 14.8.9 output. CPUID doesn't tell the two hosts apart, but execution does. On macOS 27.2, everything your table lists as SIGILL apart from RDSEED, RDPID, CLWB, ADCX and ADOX executes with correct results.
- This matches the M1 pattern already in the entry (ANDN/RDRAND fault on macOS 15.3.1 and execute on 26.6.2). The new entry might say that on the M2 the faults were seen on macOS 14.8.9 and are absent on macOS 27.2, so readers don't take it as a chip limit.
Written with AI assistance (Claude Code). I ran the builds and tests above on my machine.
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What
Adds an entry to
docs/dev/debt/relinker.mdrecording Rosetta instruction support on an M2 with macOS 14.8.9. Under macOS 14's Rosetta, most of what the M1 (macOS 26.6.2) and M5 (macOS 26.4) surveys record as executing raises SIGILL: AVX, AVX2, FMA, F16C, RDRAND, and every BMI1/BMI2 instruction except TZCNT and LZCNT. ANDN is lowered by--to-rosetta, but the rest are not, so a converted module that reaches them faults on this host. RDTSCP reports the same constant TSC_AUX (ECX = 0xAAAAAAAB).This is a separate entry rather than another sentence in the existing
--to-rosettaentry. That entry is already 1,791 characters, and thedebt-lengthcheck added in #6757 warns about entries over 1,000. The new entry is 610 characters.Method: same as #7185. Each instruction runs in its own forked x86-64 process built with
clang -arch x86_64(Apple clang 15.0.0). A process that exits normally executed the instruction; one killed by a signal did not. Each executing instruction's result was also compared with the expected value, and all matched. TZCNT(0) and LZCNT(0) both return 64, so they are not running as BSF/BSR. CPUID leaves 1, 7 and 0x80000001 were read directly under Rosetta. The encodings were checked withobjdump.Raw probe output
(For RDTSCP,
gotis ECX;wantis unused.)The overlap check could not compare #5021, #6977, #7173, #7332 and #7417, which also change
docs/dev/debt/relinker.md. I checked them by hand: none of them edits the--to-rosettaentry (#7173 adds a separate ADCX/ADOX entry). If one merges first and conflicts, I'll rebase.Tested
Documentation only. The measurements are from an Apple M2 with macOS 14.8.9, as described above.
python3 tools/check_conventions.py --base origin/mainpasses.Checklist
main; no other open PR implements the same functionsNotImplemented_nid_no_patch); silent stubs are listed under Silent stubs in their library's technical debt file.mdfiles or images added to the repository (attach them to this PR)