Parameterizable Weight-Stationary Systolic Array implemented in Verilog designed to accelerate matrix multiplication through 2D grid of Processing Elements (PEs)
- Configurable Square Array Size via Verilog parameters
- Staggered data movement
- Includes a top-level wrapper for VIO Integration
- Verified on Digilent Arty S7-25 FPGA (constraints file for Arty S7-25 included)
Consists of 2D grid of PEs with each responsible for following operations:
- Multiplying horizontal activations to PE stored weight
- Adds product to sum arriving from PE above
- Passes activation to the right and calculated sum to the bottom
This project is licensed under the MIT License.