Futil changes

[KarlJoad]

These are all the changes I made while debugging why this core would not complete a Verilator simulation. I used the provided memory files and program.

I needed to fix some Verilator lint failures, which is the slicing commit.

I needed to fix some simulation-time checks that the SystemVerilog has ifdef-ed to only run under Verilator.

At the end, I end up with a simulation problem because r_type.in has multiple drivers in a single clock cycle.

Below is a minimum transcript of what I did/was doing to reach this point.

$ pwd
~/calyx

$ ./target/debug/fud2 ./calyx-riscv/src/main.futil \
                      --from calyx \
                      -o test.exe \
                      -s sim.data=./calyx-riscv/data/simple.json \
                      --keep

$ python3 ./.fud2-working/json-dat.py \
          --from-json ./calyx-riscv/data/simple.json \
          --out_dir=sim_data/

$ ./test.exe +DATA=./sim_data +CYCLE_LIMIT=500

[sgpthomas]

I haven't looked closely at the changes yet. However, the changes seem to produce the wrong results on simple.s. Were you getting these values in the registers when you ran it? I was getting all zeros with your branch.

== registers ==
x0  zero: 0
x1    ra: xxxxxxxx
x2    sp: xxxxxxxx
x3    gp: xxxxxxxx
x4    tp: xxxxxxxx
x5    t0: 10
x6    t1: 10
x7    t2: 1
x8    fp: xxxxxxxx
x9    s1: xxxxxxxx
x10    a0: 10
x11    a1: 10
x12    a2: xxxxxxxx
x13    a3: xxxxxxxx
x14    a4: xxxxxxxx
x15    a5: xxxxxxxx
x16    a6: 0
x17    a7: 0
x18    s2: 0
x19    s3: 0
x20    s4: 0
x21    s5: 0
x22    s6: 0
x23    s7: 0
x24    s8: 0
x25    s9: 0
x26   s10: 0
x27   s11: 0
x28    t3: 0
x29    t4: 0
x30    t5: 0
x31    t6: 0

[KarlJoad]

With my branch, yes. I get that exact output.

$ fud2 riscv-to-calyx/data/simple.s --to riscv-decode --keep
ERROR:root:Memory contains the value: `0xxxxxxxxx', which is uninitialized. This happens when the Calyx design attempts to read a port that is not connected to anything. Try to generate a VCD file using `--to vcd` and look for signals that are not driven in a given cycle.
ERROR:root:Memory contains the value: `0xxxxxxxxx', which is uninitialized. This happens when the Calyx design attempts to read a port that is not connected to anything. Try to generate a VCD file using `--to vcd` and look for signals that are not driven in a given cycle.
ERROR:root:Memory contains the value: `0xxxxxxxxx', which is uninitialized. This happens when the Calyx design attempts to read a port that is not connected to anything. Try to generate a VCD file using `--to vcd` and look for signals that are not driven in a given cycle.
ERROR:root:Memory contains the value: `0xxxxxxxxx', which is uninitialized. This happens when the Calyx design attempts to read a port that is not connected to anything. Try to generate a VCD file using `--to vcd` and look for signals that are not driven in a given cycle.
ERROR:root:Memory contains the value: `0xxxxxxxxx', which is uninitialized. This happens when the Calyx design attempts to read a port that is not connected to anything. Try to generate a VCD file using `--to vcd` and look for signals that are not driven in a given cycle.
ERROR:root:Memory contains the value: `0xxxxxxxxx', which is uninitialized. This happens when the Calyx design attempts to read a port that is not connected to anything. Try to generate a VCD file using `--to vcd` and look for signals that are not driven in a given cycle.
ERROR:root:Memory contains the value: `0xxxxxxxxx', which is uninitialized. This happens when the Calyx design attempts to read a port that is not connected to anything. Try to generate a VCD file using `--to vcd` and look for signals that are not driven in a given cycle.
ERROR:root:Memory contains the value: `0xxxxxxxxx', which is uninitialized. This happens when the Calyx design attempts to read a port that is not connected to anything. Try to generate a VCD file using `--to vcd` and look for signals that are not driven in a given cycle.
ERROR:root:Memory contains the value: `0xxxxxxxxx', which is uninitialized. This happens when the Calyx design attempts to read a port that is not connected to anything. Try to generate a VCD file using `--to vcd` and look for signals that are not driven in a given cycle.
ERROR:root:Memory contains the value: `0xxxxxxxxx', which is uninitialized. This happens when the Calyx design attempts to read a port that is not connected to anything. Try to generate a VCD file using `--to vcd` and look for signals that are not driven in a given cycle.
ERROR:root:Memory contains the value: `0xxxxxxxxx', which is uninitialized. This happens when the Calyx design attempts to read a port that is not connected to anything. Try to generate a VCD file using `--to vcd` and look for signals that are not driven in a given cycle.
Took 263 cycles

== instructions ==
  0: addi x10, x0, 0
  1: addi x11, x0, 10
  2: addi x5, x0, 0
  3: addi x6, x0, 0
  4: bge x6, x11, 1c
  5: slli x7, x6, 2
  6: add x7, x10, x7
  7: lw xxx
  8: add x5, x5, x7
  9: addi x6, x6, 1
 10: J { opcode: 111, rd: 0, imm: 1042943 }
 11: addi x10, x5, 0
 12: I { opcode: 103, rd: 0, funct3: 0, rs1: 1, imm: 0 }

== registers ==
x0  zero: 0
x1    ra: xxxxxxxx
x2    sp: xxxxxxxx
x3    gp: xxxxxxxx
x4    tp: xxxxxxxx
x5    t0: 0
x6    t1: xxxxxxxx
x7    t2: 0
x8    fp: xxxxxxxx
x9    s1: xxxxxxxx
x10    a0: 0
x11    a1: 0
x12    a2: xxxxxxxx
x13    a3: xxxxxxxx
x14    a4: xxxxxxxx
x15    a5: xxxxxxxx
x16    a6: 0
x17    a7: 0
x18    s2: 0
x19    s3: 0
x20    s4: 0
x21    s5: 0
x22    s6: 0
x23    s7: 0
x24    s8: 0
x25    s9: 0
x26   s10: 0
x27   s11: 0
x28    t3: 0
x29    t4: 0
x30    t5: 0
x31    t6: 0

But this simulation is going through Icarus, while all my simulation-time errors were coming from Verilator.

[sgpthomas]

The zeros for t0, t1, t2 and a0, a1 are incorrect. They should be all 10, with exception for t2 which should be 1. Can you figure out why your implementation is not producing the correct answer?

[KarlJoad]

The incorrectness comes from the last commit (cbe67d8), because I change r_type.in in the decoder. But that is one spot where Verilator was giving me a multiple-driver issue when I tried to manually simulate with Verilator.