CmodA7_IntroVerilog

Please refer to the video link. The implementation result is like that. This could be used for validation of the board. https://www.youtube.com/watch?v=xugT-lMO_qY

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
project_video_test.cache/wt		project_video_test.cache/wt
project_video_test.hw		project_video_test.hw
project_video_test.runs		project_video_test.runs
project_video_test.srcs		project_video_test.srcs
.gitattributes		.gitattributes
LICENSE		LICENSE
README.md		README.md
project_video_test.xpr		project_video_test.xpr
test.mcs		test.mcs
test.prm		test.prm
vivado.jou		vivado.jou
vivado.log		vivado.log
vivado_pid11392.str		vivado_pid11392.str

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