Skip to content
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions pyverilator/pyverilator.py
Original file line number Diff line number Diff line change
Expand Up @@ -455,13 +455,13 @@ def search_for_signal_decl(signal_type, line):
result.group(4)) == 0:
# this is an internal signal
signal_width = int(result.group(3)) - int(result.group(4)) + 1
return (signal_name, signal_width)
return (signal_name.strip('&'), signal_width)
else:
return None
else:
# this is an input or an output
signal_width = int(result.group(3)) - int(result.group(4)) + 1
return (signal_name, signal_width)
return (signal_name.strip('&'), signal_width)
else:
return None

Expand Down
2 changes: 1 addition & 1 deletion pyverilator/verilatorcpp.py
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ def function_definitions_cpp(top_module, inputs, outputs, internal_signals, json
VL_PRINTF("- %s:%d: Verilog $finish\\n", filename, linenum); // Not VL_PRINTF_MT, already on main thread
if (Verilated::gotFinish()) {{
VL_PRINTF("- %s:%d: Second verilog $finish, exiting\\n", filename, linenum); // Not VL_PRINTF_MT, already on main thread
Verilated::flushCall();
Verilated::runFlushCallbacks();
exit(0);
}}
Verilated::gotFinish(true);
Expand Down