schemas: pci: bridge: Document the graph port #180
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robherring merged 2 commits intodevicetree-org:mainfrom Jan 13, 2026
Merged
schemas: pci: bridge: Document the graph port #180robherring merged 2 commits intodevicetree-org:mainfrom
robherring merged 2 commits intodevicetree-org:mainfrom
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This property was added to specify whether the bridge supports transitioning to D3 state (D3Cold) or not as needed by Linux. But it turns out that this information could be inferred from the existence of the supply properties in the bridge node. So this property was never used at all. So remove it. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
An external connector like M.2 could expose the PCIe interface to the plugin cards. So add the graph port to establish link between the Root Port and the connector node. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
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Hi, This series is an initial attempt to support the PCIe M.2 connectors in the kernel and devicetree binding. The PCIe M.2 connectors as defined in the PCI Express M.2 Specification are widely used in Notebooks/Tablet form factors (even in PCs). On the ACPI platforms, power to these connectors are mostly handled by the firmware/BIOS and the kernel never bothered to directly power manage them as like other PCIe connectors. But on the devicetree platforms, the kernel needs to power manage these connectors with the help of the devicetree description. But so far, there is no proper representation of the M.2 connectors in devicetree binding. This forced the developers to fake the M.2 connectors as PMU nodes [1] and fixed regulators in devicetree. So to properly support the M.2 connectors in devicetree platforms, this series introduces the devicetree binding for Mechanical Key M connector as an example and also the corresponding pwrseq driver and PCI changes in kernel to driver the connector. The Mechanical Key M connector is used to connect SSDs to the host machine over PCIe/SATA interfaces. Due to the hardware constraints, this series only adds support for driving the PCIe interface of the connector in the kernel. Also, the optional interfaces supported by the Key M connectors are not supported in the driver and left for the future enhancements. Testing ======= This series, together with the devicetree changes [2] [3] were tested on the Qualcomm X1e based Lenovo Thinkpad T14s Laptop which has the NVMe SSD connected over PCIe. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts?h=v6.18-rc4&id=d09ab685a8f51ba412d37305ea62628a01cbea57 [2] 40120d0 [3] ff6c307 Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org Cc: Stephan Gerhold <stephan.gerhold@linaro.org> Cc: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Cc: linux-pm@vger.kernel.org Cc: linux-ide@vger.kernel.org To: Bjorn Helgaas <bhelgaas@google.com> To: Manivannan Sadhasivam <mani@kernel.org> To: Rob Herring <robh@kernel.org> To: Krzysztof Kozlowski <krzk+dt@kernel.org> To: Conor Dooley <conor+dt@kernel.org> To: Bartosz Golaszewski <brgl@bgdev.pl> To: Damien Le Moal <dlemoal@kernel.org> To: Niklas Cassel <cassel@kernel.org> To: Linus Walleij <linus.walleij@linaro.org> To: Bartosz Golaszewski <brgl@kernel.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> --- Changes in v6: - EDITME: describe what is new in this series revision. - EDITME: use bulletpoints and terse descriptions. - Link to v5: https://lore.kernel.org/r/20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com Changes in v5: - used of_node_get() and devm_action to free regulators - Link to v4: https://lore.kernel.org/r/20251228-pci-m2-v4-0-5684868b0d5f@oss.qualcomm.com Changes in v4: - Added graph property to SATA in this series and PCI to dtschema: devicetree-org/dt-schema#180 - Used 'i2c-parent' instead of SMBus port - Reworded the -gpios property description - Rebased on top of v6.19-rc1 - Link to v3: https://lore.kernel.org/r/20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com Changes in v3: - Changed the VIO supply name as per dtschema - Added explicit endpoint properties to port 0 node for host I/F - Used scope based cleanup for OF node in pwrseq driver - Collected review tags - Link to v2: https://lore.kernel.org/r/20251108-pci-m2-v2-0-e8bc4d7bf42d@oss.qualcomm.com Changes in v2: - Incorporated comments from Bartosz and Frank for pwrseq and dt-binding patches, especially adding the pwrseq match() code. - Link to v1: https://lore.kernel.org/r/20251105-pci-m2-v1-0-84b5f1f1e5e8@oss.qualcomm.com --- b4-submit-tracking --- # This section is used internally by b4 prep for tracking purposes. { "series": { "revision": 6, "change-id": "20251103-pci-m2-7633631b6faa", "prefixes": [], "history": { "v1": [ "20251105-pci-m2-v1-0-84b5f1f1e5e8@oss.qualcomm.com" ], "v2": [ "20251108-pci-m2-v2-0-e8bc4d7bf42d@oss.qualcomm.com" ], "v3": [ "20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com" ], "v4": [ "20251228-pci-m2-v4-0-5684868b0d5f@oss.qualcomm.com" ], "v5": [ "20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com" ] } } }
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Jan 28, 2026
EDITME: Imported from f20260122-pci-m2-v6-0-575da9f97239@oss.qualcomm.com
Please review before sending.
Hi,
This series is an initial attempt to support the PCIe M.2 connectors in the
kernel and devicetree binding. The PCIe M.2 connectors as defined in the PCI
Express M.2 Specification are widely used in Notebooks/Tablet form factors (even
in PCs). On the ACPI platforms, power to these connectors are mostly handled by
the firmware/BIOS and the kernel never bothered to directly power manage them as
like other PCIe connectors. But on the devicetree platforms, the kernel needs to
power manage these connectors with the help of the devicetree description. But
so far, there is no proper representation of the M.2 connectors in devicetree
binding. This forced the developers to fake the M.2 connectors as PMU nodes [1]
and fixed regulators in devicetree.
So to properly support the M.2 connectors in devicetree platforms, this series
introduces the devicetree binding for Mechanical Key M connector as an example
and also the corresponding pwrseq driver and PCI changes in kernel to driver the
connector.
The Mechanical Key M connector is used to connect SSDs to the host machine over
PCIe/SATA interfaces. Due to the hardware constraints, this series only adds
support for driving the PCIe interface of the connector in the kernel.
Also, the optional interfaces supported by the Key M connectors are not
supported in the driver and left for the future enhancements.
Testing
=======
This series, together with the devicetree changes [2] [3] were tested on the
Qualcomm X1e based Lenovo Thinkpad T14s Laptop which has the NVMe SSD connected
over PCIe.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts?h=v6.18-rc4&id=d09ab685a8f51ba412d37305ea62628a01cbea57
[2] 40120d0
[3] ff6c307
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
Changes in v6:
- Used 'ports' to describe interfaces instead of endpoints in the binding
- Added GPIOs and USB to the example in binding
- Incorporated minor comments in the pwrseq driver
- Dropped the ata binding patch as it got applied
- Link to v5: https://lore.kernel.org/r/20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com
Changes in v5:
- used of_node_get() and devm_action to free regulators
- Link to v4: https://lore.kernel.org/r/20251228-pci-m2-v4-0-5684868b0d5f@oss.qualcomm.com
Changes in v4:
- Added graph property to SATA in this series and PCI to dtschema:
devicetree-org/dt-schema#180
- Used 'i2c-parent' instead of SMBus port
- Reworded the -gpios property description
- Rebased on top of v6.19-rc1
- Link to v3: https://lore.kernel.org/r/20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com
Changes in v3:
- Changed the VIO supply name as per dtschema
- Added explicit endpoint properties to port 0 node for host I/F
- Used scope based cleanup for OF node in pwrseq driver
- Collected review tags
- Link to v2: https://lore.kernel.org/r/20251108-pci-m2-v2-0-e8bc4d7bf42d@oss.qualcomm.com
Changes in v2:
- Incorporated comments from Bartosz and Frank for pwrseq and dt-binding
patches, especially adding the pwrseq match() code.
- Link to v1: https://lore.kernel.org/r/20251105-pci-m2-v1-0-84b5f1f1e5e8@oss.qualcomm.com
--- b4-submit-tracking ---
# This section is used internally by b4 prep for tracking purposes.
{
"series": {
"revision": 6,
"change-id": "20251103-pci-m2-7633631b6faa",
"prefixes": [],
"history": {
"v1": [
"20251105-pci-m2-v1-0-84b5f1f1e5e8@oss.qualcomm.com"
],
"v2": [
"20251108-pci-m2-v2-0-e8bc4d7bf42d@oss.qualcomm.com"
],
"v3": [
"20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com"
],
"v4": [
"20251228-pci-m2-v4-0-5684868b0d5f@oss.qualcomm.com"
],
"v5": [
"20260107-pci-m2-v5-0-8173d8a72641@oss.qualcomm.com"
]
}
}
}
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An external connector like M.2 could expose the PCIe interface to the plugin cards. So add the graph port to establish link between the Root Port and the connector node.