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Add missing operands to disassembly for common arm instructions (gem5#2346)
For a number of common instructions, gem5's built-in ARM disassembler doesn't print the instruction operands. This can be a bit of a headache when you don't want to use libcapstone, and are looking at instruction traces. Reproducer: test.S ``` .text .globl _start _start: ldr x30, [sp] ldr x30, [sp], gem5#16 str x30, [sp] str x30, [sp], gem5#16 ldp x10, x20, [x30] stp x10, x20, [x30] ldp w10, w20, [x30] stp w10, w20, [x30] ldp x10, x20, [x30], #-8 // post-index, negative stp x10, x20, [x30, gem5#16]! // pre-index, write-back ldp w10, w20, [x30, gem5#32] // pre-index, no write-back stp w10, w20, [x30], gem5#128 // post-index, positive dc zva, x17 dc cvac, x17 isb isb #10 dsb nsh dsb sy dsb #8 .long 0xff210110 // m5_op EXIT ``` ``` # Build binary aarch64-linux-gnu-gcc -c test.S -o test.o aarch64-linux-gnu-ld -o test.arm64 test.o -N -Ttext 0x10 -static # objdump disassembly aarch64-linux-gnu-objdump -D test.arm64 # gem5 disassembly ./build/ARM/gem5.opt configs/example/arm/baremetal.py --tarmac-gen --kernel test.arm64 | grep ' IT ' ```
2 parents 27bb878 + 925cd69 commit ff18a3d

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‎src/arch/arm/insts/macromem.cc‎

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -246,7 +246,12 @@ PairMemOp::PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
246246
bool signExt, bool exclusive, bool acrel,
247247
int64_t imm, AddrMode mode,
248248
RegIndex rn, RegIndex rt, RegIndex rt2) :
249-
PredMacroOp(mnem, machInst, __opClass)
249+
PredMacroOp(mnem, machInst, __opClass),
250+
mode(mode),
251+
rn(rn),
252+
rt(rt),
253+
rt2(rt2),
254+
imm(imm)
250255
{
251256
bool post = (mode == AddrMd_PostIndex);
252257
bool writeback = (mode != AddrMd_Offset);
@@ -1643,5 +1648,31 @@ MicroMemPairOp::generateDisassembly(
16431648
return ss.str();
16441649
}
16451650

1651+
std::string
1652+
PairMemOp::generateDisassembly(
1653+
Addr pc, const loader::SymbolTable *symtab) const
1654+
{
1655+
std::stringstream ss;
1656+
printMnemonic(ss);
1657+
printIntReg(ss, rt);
1658+
ss << ", ";
1659+
printIntReg(ss, rt2);
1660+
ss << ", [";
1661+
printIntReg(ss, rn, 64);
1662+
if (mode == AddrMd_PostIndex) {
1663+
ss << "]";
1664+
}
1665+
if (imm) {
1666+
ccprintf(ss, ", #%d", imm);
1667+
}
1668+
if (mode != AddrMd_PostIndex) {
1669+
ss << "]";
1670+
}
1671+
if (mode == AddrMd_PreIndex) {
1672+
ss << "!";
1673+
}
1674+
return ss.str();
1675+
}
1676+
16461677
} // namespace ArmISA
16471678
} // namespace gem5

‎src/arch/arm/insts/macromem.hh‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -481,10 +481,16 @@ class PairMemOp : public PredMacroOp
481481
};
482482

483483
protected:
484+
AddrMode mode;
485+
RegIndex rn, rt, rt2;
486+
int32_t imm;
484487
PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
485488
uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
486489
bool exclusive, bool acrel, int64_t imm, AddrMode mode,
487490
RegIndex rn, RegIndex rt, RegIndex rt2);
491+
492+
std::string generateDisassembly(
493+
Addr pc, const loader::SymbolTable *symtab) const override;
488494
};
489495

490496
class BigFpMemImmOp : public PredMacroOp

‎src/arch/arm/insts/mem64.cc‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -51,8 +51,7 @@ std::string
5151
SysDC64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
5252
{
5353
std::stringstream ss;
54-
printMnemonic(ss, "", false);
55-
ccprintf(ss, ", ");
54+
ss << " " << mnemonic << ", ";
5655
printIntReg(ss, base);
5756
return ss.str();
5857
}
@@ -155,9 +154,9 @@ MemoryPostIndex64::generateDisassembly(
155154
{
156155
std::stringstream ss;
157156
startDisassembly(ss);
158-
if (imm)
159-
ccprintf(ss, "], #%d", imm);
160157
ccprintf(ss, "]");
158+
if (imm)
159+
ccprintf(ss, ", #%d", imm);
161160
return ss.str();
162161
}
163162

‎src/arch/arm/insts/misc64.cc‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2643,4 +2643,38 @@ AtOp64::addressTranslation64(ThreadContext* tc,
26432643
return std::make_pair(fault, par);
26442644
}
26452645

2646+
std::string
2647+
IsbOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
2648+
{
2649+
std::stringstream ss;
2650+
printMnemonic(ss, "", false);
2651+
if (imm != 15) {
2652+
ccprintf(ss, "#%d", imm);
2653+
}
2654+
return ss.str();
2655+
}
2656+
2657+
std::string
2658+
DsbOp64::generateDisassembly(Addr pc, const loader::SymbolTable *symtab) const
2659+
{
2660+
std::stringstream ss;
2661+
ss << " " << mnemonic << " ";
2662+
switch (imm) {
2663+
case 1: ss << "OSHLD"; break;
2664+
case 2: ss << "OSHST"; break;
2665+
case 3: ss << "OSH"; break;
2666+
case 5: ss << "NSHLD"; break;
2667+
case 6: ss << "NSHST"; break;
2668+
case 7: ss << "NSH"; break;
2669+
case 9: ss << "ISHLD"; break;
2670+
case 10: ss << "ISHST"; break;
2671+
case 11: ss << "ISH"; break;
2672+
case 13: ss << "LD"; break;
2673+
case 14: ss << "ST"; break;
2674+
case 15: ss << "SY"; break;
2675+
default: ss << "#" << imm; break;
2676+
}
2677+
return ss.str();
2678+
}
2679+
26462680
} // namespace gem5

‎src/arch/arm/insts/misc64.hh‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -357,6 +357,34 @@ class AtOp64 : public MiscRegRegImmOp64
357357
BaseMMU::Mode mode, Request::Flags flags, RegVal val) const;
358358
};
359359

360+
class IsbOp64 : public ArmISA::ArmStaticInst
361+
{
362+
protected:
363+
uint64_t imm;
364+
365+
IsbOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
366+
OpClass __opClass, uint64_t _imm) :
367+
ArmISA::ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
368+
{}
369+
370+
std::string generateDisassembly(
371+
Addr pc, const loader::SymbolTable *symtab) const override;
372+
};
373+
374+
class DsbOp64 : public ArmISA::ArmStaticInst
375+
{
376+
protected:
377+
uint64_t imm;
378+
379+
DsbOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
380+
OpClass __opClass, uint64_t _imm) :
381+
ArmISA::ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
382+
{}
383+
384+
std::string generateDisassembly(
385+
Addr pc, const loader::SymbolTable *symtab) const override;
386+
};
387+
360388
} // namespace gem5
361389

362390
#endif

‎src/arch/arm/isa/formats/aarch64.isa‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -399,12 +399,12 @@ namespace Aarch64
399399
if (bits(crm, 1, 0) == 0b10) {
400400
switch (bits(crm, 3, 2)) {
401401
case 0x1: // Non-Shareable
402-
return new Dsb64Local(machInst);
402+
return new Dsb64Local(machInst, crm);
403403
case 0x0: // OuterShareable
404404
case 0x2: // InnerShareable
405405
case 0x3: // FullSystem
406406
return new Dsb64Shareable(
407-
machInst, dec.dvmEnabled);
407+
machInst, crm, dec.dvmEnabled);
408408
default:
409409
GEM5_UNREACHABLE;
410410
}
@@ -416,19 +416,19 @@ namespace Aarch64
416416
case 0x4:
417417
switch (bits(crm, 3, 2)) {
418418
case 0x1: // Non-Shareable
419-
return new Dsb64Local(machInst);
419+
return new Dsb64Local(machInst, crm);
420420
case 0x0: // OuterShareable
421421
case 0x2: // InnerShareable
422422
case 0x3: // FullSystem
423423
return new Dsb64Shareable(
424-
machInst, dec.dvmEnabled);
424+
machInst, crm, dec.dvmEnabled);
425425
default:
426426
GEM5_UNREACHABLE;
427427
}
428428
case 0x5:
429429
return new Dmb64(machInst);
430430
case 0x6:
431-
return new Isb64(machInst);
431+
return new Isb64(machInst, crm);
432432
default:
433433
return new Unknown64(machInst);
434434
}

‎src/arch/arm/isa/insts/misc64.isa‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -188,17 +188,17 @@ let {{
188188
decoder_output += BasicConstructor64.subst(unknown64Iop)
189189
exec_output += BasicExecute.subst(unknown64Iop)
190190

191-
isbIop = ArmInstObjParams("isb", "Isb64", "ArmStaticInst", "",
191+
isbIop = ArmInstObjParams("isb", "Isb64", "IsbOp64", "",
192192
['IsSquashAfter'])
193-
header_output += BasicDeclare.subst(isbIop)
194-
decoder_output += BasicConstructor64.subst(isbIop)
193+
header_output += ImmOp64Declare.subst(isbIop)
194+
decoder_output += ImmOp64Constructor.subst(isbIop)
195195
exec_output += BasicExecute.subst(isbIop)
196196

197-
dsbLocalIop = ArmInstObjParams("dsb", "Dsb64Local", "ArmStaticInst", "",
197+
dsbLocalIop = ArmInstObjParams("dsb", "Dsb64Local", "DsbOp64", "",
198198
['IsReadBarrier', 'IsWriteBarrier',
199199
'IsSerializeAfter'])
200-
header_output += BasicDeclare.subst(dsbLocalIop)
201-
decoder_output += BasicConstructor64.subst(dsbLocalIop)
200+
header_output += ImmOp64Declare.subst(dsbLocalIop)
201+
decoder_output += ImmOp64Constructor.subst(dsbLocalIop)
202202
exec_output += BasicExecute.subst(dsbLocalIop)
203203

204204
dvmCode = '''
@@ -215,7 +215,7 @@ let {{
215215
PendingDvm = false;
216216
}
217217
'''
218-
dsbShareableIop = ArmInstObjParams("dsb", "Dsb64Shareable", "ArmStaticInst",
218+
dsbShareableIop = ArmInstObjParams("dsb", "Dsb64Shareable", "DsbOp64",
219219
{ "code" : "", "dvm_code" : dvmCode },
220220
['IsReadBarrier', 'IsWriteBarrier',
221221
'IsSerializeAfter'])

‎src/arch/arm/isa/templates/misc64.isa‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -331,7 +331,7 @@ def template DvmDeclare {{
331331

332332
public:
333333
/// Constructor.
334-
%(class_name)s(ExtMachInst machInst, bool dvm_enabled);
334+
%(class_name)s(ExtMachInst machInst, uint64_t imm, bool dvm_enabled);
335335
Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
336336
Fault completeAcc(PacketPtr, ExecContext *,
337337
trace::InstRecord *) const override;
@@ -368,8 +368,9 @@ def template AtConstructor {{
368368
}};
369369

370370
def template DvmConstructor {{
371-
%(class_name)s::%(class_name)s(ExtMachInst machInst, bool dvm_enabled) :
372-
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s),
371+
%(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t imm,
372+
bool dvm_enabled) :
373+
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm),
373374
dvmEnabled(dvm_enabled)
374375
{
375376
%(set_reg_idx_arr)s;

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