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@kroening kroening commented Apr 23, 2025

This introduces a type for Verilog SVA properties to distinguish properties from state predicates and sequences.

@kroening kroening force-pushed the verilog_sva_property_type branch from 9e75065 to d6241f6 Compare April 23, 2025 16:40
@kroening kroening force-pushed the verilog_sva_property_type branch 4 times, most recently from e0570e9 to 9b2f517 Compare May 13, 2025 19:58
@kroening kroening force-pushed the verilog_sva_property_type branch 2 times, most recently from 0905cf1 to 7b91923 Compare June 5, 2025 16:47
@kroening kroening force-pushed the verilog_sva_property_type branch 6 times, most recently from 0631311 to e1ca37b Compare July 9, 2025 16:57
This introduces a type for Verilog SVA properties to distinguish properties
from state predicates and sequences.
@kroening kroening force-pushed the verilog_sva_property_type branch from e1ca37b to ca996d1 Compare July 9, 2025 17:51
@kroening kroening marked this pull request as ready for review July 9, 2025 20:26
@tautschnig tautschnig merged commit 0c80385 into main Jul 16, 2025
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@tautschnig tautschnig deleted the verilog_sva_property_type branch July 16, 2025 10:11
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3 participants