Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add support for Add Sve.GatherVectorUInt*ZeroExtendFirstFaulting() #105030

Merged
Merged
Show file tree
Hide file tree
Changes from 69 commits
Commits
Show all changes
71 commits
Select commit Hold shift + click to select a range
d0efc9e
Initial work
TIHan Jul 2, 2024
42148fd
Merge remote-tracking branch 'upstream/main' into sve-ffr-part1
TIHan Jul 2, 2024
a7773ac
FirstFaulting partially works
TIHan Jul 2, 2024
76b42bd
Added template
TIHan Jul 2, 2024
bb01e37
Trying to test first-faulting behavior
TIHan Jul 4, 2024
a602b24
Using BoundedMemory to test FirstFaulting behavior for LoadVector.
TIHan Jul 6, 2024
60d410a
Fix size in validation
TIHan Jul 6, 2024
aee87d7
Added more helper functions. Added conditional select tests for LoadV…
TIHan Jul 8, 2024
7f3bb3c
Added first-faulting behavior tests for GatherVectorFirstFaulting
TIHan Jul 8, 2024
d952ff1
Merging with main
TIHan Jul 8, 2024
3923946
Added GetFfr suffix-style APIs
TIHan Jul 8, 2024
461b6a3
Fixing GatherVector tests
TIHan Jul 8, 2024
d5b8675
Formatting
TIHan Jul 8, 2024
07833e3
Feedback
TIHan Jul 9, 2024
ce5a9bd
Merge remote-tracking branch 'upstream/main' into sve-ffr-part1
TIHan Jul 9, 2024
05fb46d
Feedback
TIHan Jul 9, 2024
c63f878
Ensure the P/Invokes are blittable
tannergooding Jul 10, 2024
a4533fe
Merging
TIHan Jul 11, 2024
72d1dea
Merge remote-tracking branch 'upstream/main' into sve-ffr-part1
TIHan Jul 12, 2024
6c28927
Fix build
TIHan Jul 13, 2024
fb2012e
Remove checking for zeroes after the fault
TIHan Jul 13, 2024
aca6759
Added GatherVectorFirstFaultingVectorBases test template, but current…
TIHan Jul 16, 2024
d781fdc
Mark GetFfr methods as side-effectful
TIHan Jul 16, 2024
405fad7
Add Sve.GatherVectorUInt*ZeroExtendFirstFaulting()
SwapnilGaikwad Jul 15, 2024
7d952d9
Add firstFaultingLoad test for VectorBases
SwapnilGaikwad Jul 17, 2024
b760823
Remove redundant spaces
SwapnilGaikwad Jul 17, 2024
35f2fa9
Add remaining Sve.GatherVectorFirstFaulting()
SwapnilGaikwad Jul 19, 2024
a73fe35
Verifying expected fault result. Test weaks.
TIHan Jul 19, 2024
81882a4
Merging with main
TIHan Jul 19, 2024
ad5ec2e
Fix build
TIHan Jul 20, 2024
19d07a9
Fix intrinsic order
SwapnilGaikwad Jul 20, 2024
54528d5
Merge will-ffr changes
SwapnilGaikwad Jul 20, 2024
d48812a
Fix GetFFR type
SwapnilGaikwad Jul 22, 2024
c36ca1a
Fix formatting issues
SwapnilGaikwad Jul 22, 2024
74dbdde
Fix PoisonPage configuration while creating BoundedMemory
SwapnilGaikwad Jul 23, 2024
6f8bc68
Use mmap() instead of memalign() for memory allocation
SwapnilGaikwad Jul 23, 2024
0f88d8e
Add tracking of FFR register
kunalspathak Jul 19, 2024
10cf342
Change condition for PhysReg
kunalspathak Jul 23, 2024
e7507bb
jit format
kunalspathak Jul 23, 2024
aef79cd
Fix PoisonPage configuration while creating BoundedMemory
SwapnilGaikwad Jul 23, 2024
690e7ad
Use mmap() instead of memalign() for memory allocation
SwapnilGaikwad Jul 23, 2024
b23fac7
review feedback
kunalspathak Jul 23, 2024
0c8b688
unspill for LoadVectorFirstFaulting as well
kunalspathak Jul 23, 2024
3184b77
Merging with Kunal's FFR changes
TIHan Jul 24, 2024
ac4ef47
Show error codes on failing failure
SwapnilGaikwad Jul 24, 2024
5bb0b3d
Show error codes on failing failure
SwapnilGaikwad Jul 24, 2024
823e847
Merging with main
TIHan Jul 26, 2024
86715e5
Feedback
TIHan Jul 26, 2024
8b0f000
Feedback
TIHan Jul 26, 2024
044dbda
Feedback
TIHan Jul 26, 2024
0655d4b
Feedback
TIHan Jul 26, 2024
89ac678
Merge Will's FFR changes
SwapnilGaikwad Jul 26, 2024
1a4c759
Handle FFR correctly
kunalspathak Jul 26, 2024
373d194
reuse some of the code
kunalspathak Jul 26, 2024
dba852c
Incorporate changes to preserve FFR correctly
SwapnilGaikwad Jul 26, 2024
06fc760
Handle the special effect for SetFfr
kunalspathak Jul 26, 2024
8788c5b
some fixes + test coverage
kunalspathak Jul 26, 2024
fcc3907
do not zero init lvaFfrRegister
kunalspathak Jul 26, 2024
dd4cad2
reverted local change
kunalspathak Jul 26, 2024
561faed
fix build break
kunalspathak Jul 26, 2024
f7c1ef6
Fix the arg count for GatherVector*firstFaulting in intrinsics table
SwapnilGaikwad Jul 26, 2024
c32a200
Merge main
SwapnilGaikwad Aug 8, 2024
5bba48f
Merge main
SwapnilGaikwad Aug 8, 2024
c21c773
Fix the formatting of a comment causing build failure
SwapnilGaikwad Aug 9, 2024
1e77468
Merge main
SwapnilGaikwad Aug 9, 2024
206ae4e
Fix unintentional change
SwapnilGaikwad Aug 9, 2024
4242ec7
Merge main
SwapnilGaikwad Aug 13, 2024
91e8d63
Use a template for byte offset
SwapnilGaikwad Aug 13, 2024
fb54845
Merge main
SwapnilGaikwad Aug 13, 2024
6737258
Update HW_Flag_SpecialSideEffectMask to HW_Flag_SpecialSideEffect_Oth…
SwapnilGaikwad Aug 13, 2024
81d985f
Merge main
SwapnilGaikwad Aug 13, 2024
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
36 changes: 28 additions & 8 deletions src/coreclr/jit/gentree.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -26680,16 +26680,26 @@ bool GenTreeHWIntrinsic::OperIsMemoryLoad(GenTree** pAddr) const

case NI_Sve_GatherVector:
case NI_Sve_GatherVectorByteZeroExtend:
case NI_Sve_GatherVectorByteZeroExtendFirstFaulting:
case NI_Sve_GatherVectorFirstFaulting:
case NI_Sve_GatherVectorInt16SignExtend:
case NI_Sve_GatherVectorInt16SignExtendFirstFaulting:
case NI_Sve_GatherVectorInt16WithByteOffsetsSignExtend:
case NI_Sve_GatherVectorInt16WithByteOffsetsSignExtendFirstFaulting:
case NI_Sve_GatherVectorInt32SignExtend:
case NI_Sve_GatherVectorInt32SignExtendFirstFaulting:
case NI_Sve_GatherVectorInt32WithByteOffsetsSignExtend:
case NI_Sve_GatherVectorInt32WithByteOffsetsSignExtendFirstFaulting:
case NI_Sve_GatherVectorSByteSignExtend:
case NI_Sve_GatherVectorSByteSignExtendFirstFaulting:
case NI_Sve_GatherVectorUInt16WithByteOffsetsZeroExtend:
case NI_Sve_GatherVectorUInt16WithByteOffsetsZeroExtendFirstFaulting:
case NI_Sve_GatherVectorUInt16ZeroExtend:
case NI_Sve_GatherVectorUInt16ZeroExtendFirstFaulting:
case NI_Sve_GatherVectorUInt32WithByteOffsetsZeroExtend:
case NI_Sve_GatherVectorUInt32WithByteOffsetsZeroExtendFirstFaulting:
case NI_Sve_GatherVectorUInt32ZeroExtend:
case NI_Sve_GatherVectorUInt32ZeroExtendFirstFaulting:
case NI_Sve_GatherVectorWithByteOffsetFirstFaulting:
case NI_Sve_GatherVectorWithByteOffsets:
case NI_Sve_LoadVector:
Expand Down Expand Up @@ -26811,14 +26821,24 @@ bool GenTreeHWIntrinsic::OperIsMemoryLoad(GenTree** pAddr) const
{
#ifdef TARGET_ARM64
static_assert_no_msg(
AreContiguous(NI_Sve_GatherVector, NI_Sve_GatherVectorByteZeroExtend, NI_Sve_GatherVectorFirstFaulting,
NI_Sve_GatherVectorInt16SignExtend, NI_Sve_GatherVectorInt16WithByteOffsetsSignExtend,
NI_Sve_GatherVectorInt32SignExtend, NI_Sve_GatherVectorInt32WithByteOffsetsSignExtend,
NI_Sve_GatherVectorSByteSignExtend, NI_Sve_GatherVectorUInt16WithByteOffsetsZeroExtend,
NI_Sve_GatherVectorUInt16ZeroExtend, NI_Sve_GatherVectorUInt32WithByteOffsetsZeroExtend,
NI_Sve_GatherVectorUInt32ZeroExtend));
assert(varTypeIsI(addr) || (varTypeIsSIMD(addr) && ((intrinsicId >= NI_Sve_GatherVector) &&
(intrinsicId <= NI_Sve_GatherVectorUInt32ZeroExtend))));
AreContiguous(NI_Sve_GatherVector, NI_Sve_GatherVectorByteZeroExtend,
NI_Sve_GatherVectorByteZeroExtendFirstFaulting, NI_Sve_GatherVectorFirstFaulting,
NI_Sve_GatherVectorInt16SignExtend, NI_Sve_GatherVectorInt16SignExtendFirstFaulting,
NI_Sve_GatherVectorInt16WithByteOffsetsSignExtend,
NI_Sve_GatherVectorInt16WithByteOffsetsSignExtendFirstFaulting,
NI_Sve_GatherVectorInt32SignExtend, NI_Sve_GatherVectorInt32SignExtendFirstFaulting,
NI_Sve_GatherVectorInt32WithByteOffsetsSignExtend,
NI_Sve_GatherVectorInt32WithByteOffsetsSignExtendFirstFaulting,
NI_Sve_GatherVectorSByteSignExtend, NI_Sve_GatherVectorSByteSignExtendFirstFaulting,
NI_Sve_GatherVectorUInt16WithByteOffsetsZeroExtend,
NI_Sve_GatherVectorUInt16WithByteOffsetsZeroExtendFirstFaulting,
NI_Sve_GatherVectorUInt16ZeroExtend, NI_Sve_GatherVectorUInt16ZeroExtendFirstFaulting,
NI_Sve_GatherVectorUInt32WithByteOffsetsZeroExtend,
NI_Sve_GatherVectorUInt32WithByteOffsetsZeroExtendFirstFaulting,
NI_Sve_GatherVectorUInt32ZeroExtend, NI_Sve_GatherVectorUInt32ZeroExtendFirstFaulting));
assert(varTypeIsI(addr) ||
(varTypeIsSIMD(addr) && ((intrinsicId >= NI_Sve_GatherVector) &&
(intrinsicId <= NI_Sve_GatherVectorUInt32ZeroExtendFirstFaulting))));
#else
assert(varTypeIsI(addr));
#endif
Expand Down
10 changes: 10 additions & 0 deletions src/coreclr/jit/hwintrinsic.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2175,18 +2175,28 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
#elif defined(TARGET_ARM64)
case NI_Sve_GatherVector:
case NI_Sve_GatherVectorByteZeroExtend:
case NI_Sve_GatherVectorByteZeroExtendFirstFaulting:
case NI_Sve_GatherVectorFirstFaulting:
case NI_Sve_GatherVectorInt16SignExtend:
case NI_Sve_GatherVectorInt16SignExtendFirstFaulting:
case NI_Sve_GatherVectorInt16WithByteOffsetsSignExtend:
case NI_Sve_GatherVectorInt16WithByteOffsetsSignExtendFirstFaulting:
case NI_Sve_GatherVectorInt32SignExtend:
case NI_Sve_GatherVectorInt32SignExtendFirstFaulting:
case NI_Sve_GatherVectorInt32WithByteOffsetsSignExtend:
case NI_Sve_GatherVectorInt32WithByteOffsetsSignExtendFirstFaulting:
case NI_Sve_GatherVectorSByteSignExtend:
case NI_Sve_GatherVectorSByteSignExtendFirstFaulting:
case NI_Sve_GatherVectorUInt16WithByteOffsetsZeroExtend:
case NI_Sve_GatherVectorUInt16WithByteOffsetsZeroExtendFirstFaulting:
case NI_Sve_GatherVectorUInt16ZeroExtend:
case NI_Sve_GatherVectorUInt16ZeroExtendFirstFaulting:
case NI_Sve_GatherVectorUInt32WithByteOffsetsZeroExtend:
case NI_Sve_GatherVectorUInt32WithByteOffsetsZeroExtendFirstFaulting:
case NI_Sve_GatherVectorUInt32ZeroExtend:
case NI_Sve_GatherVectorWithByteOffsetFirstFaulting:
case NI_Sve_GatherVectorWithByteOffsets:
case NI_Sve_GatherVectorUInt32ZeroExtendFirstFaulting:
assert(varTypeIsSIMD(op3->TypeGet()));
if (numArgs == 3)
{
Expand Down
15 changes: 14 additions & 1 deletion src/coreclr/jit/hwintrinsiccodegenarm64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2097,7 +2097,17 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
break;
}

case NI_Sve_GatherVectorByteZeroExtendFirstFaulting:
case NI_Sve_GatherVectorFirstFaulting:
case NI_Sve_GatherVectorInt16SignExtendFirstFaulting:
case NI_Sve_GatherVectorInt16WithByteOffsetsSignExtendFirstFaulting:
case NI_Sve_GatherVectorInt32SignExtendFirstFaulting:
case NI_Sve_GatherVectorInt32WithByteOffsetsSignExtendFirstFaulting:
case NI_Sve_GatherVectorSByteSignExtendFirstFaulting:
case NI_Sve_GatherVectorUInt16WithByteOffsetsZeroExtendFirstFaulting:
case NI_Sve_GatherVectorUInt16ZeroExtendFirstFaulting:
case NI_Sve_GatherVectorUInt32WithByteOffsetsZeroExtendFirstFaulting:
case NI_Sve_GatherVectorUInt32ZeroExtendFirstFaulting:
{
if (node->GetAuxiliaryType() == TYP_UNKNOWN)
{
Expand All @@ -2122,6 +2132,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
GetEmitter()->emitIns_R(INS_sve_wrffr, emitSize, op4Reg, opt);
}
}

FALLTHROUGH;
}
case NI_Sve_GatherVector:
Expand All @@ -2144,7 +2155,9 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
emitAttr baseSize = emitActualTypeSize(intrin.baseType);
bool isLoadingBytes =
((ins == INS_sve_ld1b) || (ins == INS_sve_ld1sb) || (ins == INS_sve_ldff1b) ||
(ins == INS_sve_ldff1sb) || (intrin.id == NI_Sve_GatherVectorWithByteOffsetFirstFaulting));
(ins == INS_sve_ldff1sb) || (intrin.id == NI_Sve_GatherVectorWithByteOffsetFirstFaulting) ||
(intrin.id == NI_Sve_GatherVectorUInt32WithByteOffsetsZeroExtendFirstFaulting) ||
(intrin.id == NI_Sve_GatherVectorUInt16WithByteOffsetsZeroExtendFirstFaulting));
insScalableOpts sopt = INS_SCALABLE_OPTS_NONE;

if (baseSize == EA_4BYTE)
Expand Down
Loading
Loading