[Wasm RyuJit] Enable Hardware Intrinsics

src/coreclr/crossgen-corelib.proj

@@ -157,7 +157,7 @@
       <CrossGenDllCmd>$(CrossGenDllCmd) -r:$([MSBuild]::NormalizePath('$(BinDir)', 'IL', '*.dll'))</CrossGenDllCmd>
       <CrossGenDllCmd>$(CrossGenDllCmd) --targetarch:$(TargetArchitecture)</CrossGenDllCmd>
       <CrossGenDllCmd Condition="'$(PublishReadyToRunContainerFormat)' != ''">$(CrossGenDllCmd) --obj-format:$(PublishReadyToRunContainerFormat)</CrossGenDllCmd>
-      <CrossGenDllCmd Condition="'$(PublishReadyToRunContainerFormat)' == 'wasm'">$(CrossGenDllCmd) --codegenopt:JitWasmNyiToR2RUnsupported=1</CrossGenDllCmd>
+      <CrossGenDllCmd Condition="'$(PublishReadyToRunContainerFormat)' == 'wasm'">$(CrossGenDllCmd) --codegenopt:JitWasmNyiToR2RUnsupported=1 --codegenopt:JitWasmSimdNyiToR2RUnsupported=1 </CrossGenDllCmd>
       <CrossGenDllCmd Condition="'$(UseComposite)' == 'true'">$(CrossGenDllCmd) --composite</CrossGenDllCmd>
       <CrossGenDllCmd>$(CrossGenDllCmd) --targetos:$(TargetOS)</CrossGenDllCmd>
       <CrossGenDllCmd Condition="'$(UsingToolIbcOptimization)' != 'true' and '$(EnableNgenOptimization)' == 'true'">$(CrossGenDllCmd) -m:$(MergedMibcPath) --embed-pgo-data</CrossGenDllCmd>

src/coreclr/inc/corinfoinstructionset.h

@@ -61,6 +61,11 @@ enum CORINFO_InstructionSet
     InstructionSet_Zbb=3,
     InstructionSet_Zbs=4,
 #endif // TARGET_RISCV64
+#ifdef TARGET_WASM
+    InstructionSet_WasmBase=1,
+    InstructionSet_PackedSimd=2,
+    InstructionSet_Vector128=3,
+#endif // TARGET_WASM
 #ifdef TARGET_AMD64
     InstructionSet_X86Base=1,
     InstructionSet_AVX=2,
@@ -284,6 +289,8 @@ struct CORINFO_InstructionSetFlags
 #endif // TARGET_ARM64
 #ifdef TARGET_RISCV64
 #endif // TARGET_RISCV64
+#ifdef TARGET_WASM
+#endif // TARGET_WASM
 #ifdef TARGET_AMD64
         if (HasInstructionSet(InstructionSet_X86Base))
             AddInstructionSet(InstructionSet_X86Base_X64);
@@ -448,6 +455,12 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
         if (resultflags.HasInstructionSet(InstructionSet_Zbs) && !resultflags.HasInstructionSet(InstructionSet_RiscV64Base))
             resultflags.RemoveInstructionSet(InstructionSet_Zbs);
 #endif // TARGET_RISCV64
+#ifdef TARGET_WASM
+        if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_PackedSimd))
+            resultflags.RemoveInstructionSet(InstructionSet_Vector128);
+        if (resultflags.HasInstructionSet(InstructionSet_PackedSimd) && !resultflags.HasInstructionSet(InstructionSet_WasmBase))
+            resultflags.RemoveInstructionSet(InstructionSet_PackedSimd);
+#endif // TARGET_WASM
 #ifdef TARGET_AMD64
         if (resultflags.HasInstructionSet(InstructionSet_X86Base) && !resultflags.HasInstructionSet(InstructionSet_X86Base_X64))
             resultflags.RemoveInstructionSet(InstructionSet_X86Base);
@@ -742,6 +755,14 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
         case InstructionSet_Zbs :
             return "Zbs";
 #endif // TARGET_RISCV64
+#ifdef TARGET_WASM
+        case InstructionSet_WasmBase :
+            return "WasmBase";
+        case InstructionSet_PackedSimd :
+            return "PackedSimd";
+        case InstructionSet_Vector128 :
+            return "Vector128";
+#endif // TARGET_WASM
 #ifdef TARGET_AMD64
         case InstructionSet_X86Base :
             return "X86Base";
@@ -943,6 +964,10 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
         case READYTORUN_INSTRUCTION_Zbb: return InstructionSet_Zbb;
         case READYTORUN_INSTRUCTION_Zbs: return InstructionSet_Zbs;
 #endif // TARGET_RISCV64
+#ifdef TARGET_WASM
+        case READYTORUN_INSTRUCTION_WasmBase: return InstructionSet_WasmBase;
+        case READYTORUN_INSTRUCTION_PackedSimd: return InstructionSet_PackedSimd;
+#endif // TARGET_WASM
 #ifdef TARGET_AMD64
         case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base;
         case READYTORUN_INSTRUCTION_Sse: return InstructionSet_X86Base;

src/coreclr/inc/jiteeversionguid.h

@@ -37,11 +37,11 @@
 
 #include <minipal/guid.h>
 
-constexpr GUID JITEEVersionIdentifier = { /* 59df85b8-c0fd-4e40-aea1-68cb2cd916cc */
-    0x59df85b8,
-    0xc0fd,
-    0x4e40,
-    {0xae, 0xa1, 0x68, 0xcb, 0x2c, 0xd9, 0x16, 0xcc}
+constexpr GUID JITEEVersionIdentifier = { /* bc67df92-da28-4e13-ba8d-4abcb0fcb75f */
+    0xbc67df92,
+    0xda28,
+    0x4e13,
+    {0xba, 0x8d, 0x4a, 0xbc, 0xb0, 0xfc, 0xb7, 0x5f}
   };
 
 #endif // JIT_EE_VERSIONING_GUID_H

src/coreclr/inc/readytoruninstructionset.h

@@ -98,6 +98,8 @@ enum ReadyToRunInstructionSet
     READYTORUN_INSTRUCTION_SveAes=88,
     READYTORUN_INSTRUCTION_SveSha3=89,
     READYTORUN_INSTRUCTION_SveSm4=90,
+    READYTORUN_INSTRUCTION_WasmBase=91,
+    READYTORUN_INSTRUCTION_PackedSimd=92,
 
 };
 

src/coreclr/jit/CMakeLists.txt

@@ -83,6 +83,11 @@ function(create_standalone_jit)
     target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_HW_INTRINSICS)
     target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_MASKED_HW_INTRINSICS)
   endif ()
+
+  if (TARGETDETAILS_ARCH STREQUAL "wasm")
+    target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_SIMD)
+    target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_HW_INTRINSICS)
+  endif ()
 endfunction()
 
 if (CLR_CMAKE_TARGET_ARCH_AMD64 OR CLR_CMAKE_TARGET_ARCH_ARM64 OR CLR_CMAKE_TARGET_ARCH_I386)
@@ -305,9 +310,12 @@ set( JIT_WASM_SOURCES
   codegenwasm.cpp
   emitwasm.cpp
   fgwasm.cpp
+  hwintrinsicwasm.cpp
+  hwintrinsiccodegenwasm.cpp
   lowerwasm.cpp
   regallocwasm.cpp
   registeropswasm.cpp
+  simd.cpp
   targetwasm.cpp
   unwindwasm.cpp
 )
@@ -501,6 +509,7 @@ set( JIT_WASM_HEADERS
     instrswasm.h
     registerwasm.h
     fgwasm.h
+    hwintrinsiclistwasm.h
 )
 
 set ( JITSHARED_SOURCES

src/coreclr/jit/abi.cpp

@@ -122,6 +122,9 @@ var_types ABIPassingSegment::GetRegisterType() const
                 return TYP_FLOAT;
             case 8:
                 return TYP_DOUBLE;
+#if defined(FEATURE_SIMD) && defined(TARGET_WASM)
+            case 12:
+#endif
 #ifdef FEATURE_SIMD
             case 16:
                 return TYP_SIMD16;

src/coreclr/jit/assertionprop.cpp

@@ -333,6 +333,8 @@ bool IntegralRange::Contains(int64_t value) const
                 case NI_ArmBase_LeadingZeroCount:
                 case NI_ArmBase_Arm64_LeadingZeroCount:
                 case NI_ArmBase_Arm64_LeadingSignCount:
+#elif defined(TARGET_WASM)
+                // TODO-WASM: See if we can support CTZ/CLZ ranges here
 #else
 #error Unsupported platform
 #endif

src/coreclr/jit/codegen.h

@@ -783,6 +783,8 @@ class CodeGen final : public CodeGenInterface
     void genSetRegToConst(regNumber targetReg, var_types targetType, GenTree* tree);
 #if defined(FEATURE_SIMD)
     void genSetRegToConst(regNumber targetReg, var_types targetType, simd_t* val);
+#endif
+#if defined(FEATURE_SIMD) && defined(FEATURE_MASKED_HW_INTRINSICS)
     void genSetRegToConst(regNumber targetReg, var_types targetType, simdmask_t* val);
 #endif
     void genLoadLocalIntoReg(regNumber targetReg, unsigned lclNum);

src/coreclr/jit/codegenlinear.cpp

@@ -1819,7 +1819,6 @@ void CodeGen::genConsumeOperands(GenTreeOp* tree)
     }
 }
 
-#ifndef TARGET_WASM
 #if defined(FEATURE_SIMD) || defined(FEATURE_HW_INTRINSICS)
 //------------------------------------------------------------------------
 // genConsumeOperands: Do liveness update for the operands of a multi-operand node,
@@ -1840,6 +1839,7 @@ void CodeGen::genConsumeMultiOpOperands(GenTreeMultiOp* tree)
 }
 #endif // defined(FEATURE_SIMD) || defined(FEATURE_HW_INTRINSICS)
 
+#ifndef TARGET_WASM
 //------------------------------------------------------------------------
 // genConsumePutStructArgStk: Do liveness update for the operands of a PutArgStk node.
 //                      Also loads in the right register the addresses of the

src/coreclr/jit/compiler.h

@@ -3992,9 +3992,12 @@ class Compiler
 
 #if defined(FEATURE_HW_INTRINSICS)
     GenTree* gtFoldExprHWIntrinsic(GenTreeHWIntrinsic* tree);
-    GenTreeMskCon* gtFoldExprConvertVecCnsToMask(GenTreeHWIntrinsic* tree, GenTreeVecCon* vecCon);
 #endif // FEATURE_HW_INTRINSICS
 
+#if defined(FEATURE_HW_INTRINSICS) && defined(FEATURE_MASKED_HW_INTRINSICS)
+    GenTreeMskCon* gtFoldExprConvertVecCnsToMask(GenTreeHWIntrinsic* tree, GenTreeVecCon* vecCon);
+#endif // FEATURE_MASKED_HW_INTRINSICS
+
     // Options to control behavior of gtTryRemoveBoxUpstreamEffects
     enum BoxRemovalOptions
     {
@@ -10215,6 +10218,9 @@ class Compiler
 
                 return FP_REGSIZE_BYTES;
             }
+#elif defined(TARGET_WASM)
+        // TODO-WASM: Verify if we need a more complicated condition here
+        return FP_REGSIZE_BYTES;
 #else
         assert(!"getVectorTByteLength() unimplemented on target arch");
         unreached();
@@ -10245,7 +10251,7 @@ class Compiler
         {
             return XMM_REGSIZE_BYTES;
         }
-#elif defined(TARGET_ARM64)
+#elif defined(TARGET_ARM64) || defined(TARGET_WASM)
         return FP_REGSIZE_BYTES;
 #else
         assert(!"getMaxVectorByteLength() unimplemented on target arch");
@@ -10343,7 +10349,7 @@ class Compiler
 
         // Return 0 if size is even less than XMM, otherwise - XMM
         return (size >= XMM_REGSIZE_BYTES) ? XMM_REGSIZE_BYTES : 0;
-#elif defined(TARGET_ARM64)
+#elif defined(TARGET_ARM64) || defined(TARGET_WASM)
         assert(getMaxVectorByteLength() == FP_REGSIZE_BYTES);
         return (size >= FP_REGSIZE_BYTES) ? FP_REGSIZE_BYTES : 0;
 #else

src/coreclr/jit/error.h

@@ -169,6 +169,7 @@ extern void notYetImplemented(const char* msg, const char* file, unsigned line);
 #define NYI_LOONGARCH64(msg) do { } while (0)
 #define NYI_RISCV64(msg) do { } while (0)
 #define NYI_WASM(msg) do { } while (0)
+#define NYI_WASM_SIMD(msg) do { } while (0)
 
 #elif defined(TARGET_X86)
 
@@ -179,6 +180,7 @@ extern void notYetImplemented(const char* msg, const char* file, unsigned line);
 #define NYI_LOONGARCH64(msg) do { } while (0)
 #define NYI_RISCV64(msg) do { } while (0)
 #define NYI_WASM(msg) do { } while (0)
+#define NYI_WASM_SIMD(msg) do { } while (0)
 
 #elif defined(TARGET_ARM)
 
@@ -189,6 +191,7 @@ extern void notYetImplemented(const char* msg, const char* file, unsigned line);
 #define NYI_LOONGARCH64(msg) do { } while (0)
 #define NYI_RISCV64(msg) do { } while (0)
 #define NYI_WASM(msg) do { } while (0)
+#define NYI_WASM_SIMD(msg) do { } while (0)
 
 #elif defined(TARGET_ARM64)
 
@@ -199,6 +202,7 @@ extern void notYetImplemented(const char* msg, const char* file, unsigned line);
 #define NYI_LOONGARCH64(msg) do { } while (0)
 #define NYI_RISCV64(msg) do { } while (0)
 #define NYI_WASM(msg) do { } while (0)
+#define NYI_WASM_SIMD(msg) do { } while (0)
 
 #elif defined(TARGET_LOONGARCH64)
 #define NYI_AMD64(msg)  do { } while (0)
@@ -208,6 +212,7 @@ extern void notYetImplemented(const char* msg, const char* file, unsigned line);
 #define NYI_LOONGARCH64(msg) NYIRAW("NYI_LOONGARCH64: " msg)
 #define NYI_RISCV64(msg) do { } while (0)
 #define NYI_WASM(msg) do { } while (0)
+#define NYI_WASM_SIMD(msg) do { } while (0)
 
 #elif defined(TARGET_RISCV64)
 #define NYI_AMD64(msg)  do { } while (0)
@@ -217,6 +222,7 @@ extern void notYetImplemented(const char* msg, const char* file, unsigned line);
 #define NYI_LOONGARCH64(msg) do { } while (0)
 #define NYI_RISCV64(msg) NYIRAW("NYI_RISCV64: " msg)
 #define NYI_WASM(msg) do { } while (0)
+#define NYI_WASM_SIMD(msg) do { } while (0)
 
 #elif defined(TARGET_WASM)
 #define NYI_AMD64(msg)  do { } while (0)
@@ -230,6 +236,10 @@ extern void notYetImplemented(const char* msg, const char* file, unsigned line);
    { JITDUMP("NYI_WASM: " msg); implReadyToRunUnsupported(); } \
    else { NYIRAW("NYI_WASM: " msg); } } while (0)
 
+#define NYI_WASM_SIMD(msg) do { if (JitConfig.JitWasmSimdNyiToR2RUnsupported() > 0) \
+   { JITDUMP("NYI_WASM_SIMD: " msg); implReadyToRunUnsupported(); } \
+   else { NYIRAW("NYI_WASM_SIMD: " msg); } } while (0)
+
 #else
 
 #error "Unknown platform, not x86, ARM, LOONGARCH64, AMD64, or RISCV64?"