SCR1
SCR1 is instantiated with a custom wrapper module. It internally connects the core with the debug module and exposes AXI, DMI and the few necessary auxiliary ports such as reset and clock signals. SCR1 features separate instruction and data memory ports. The data memory segment includes DMA and RVController, just as in the other cores.
SCR1 supports burst read/write access and access via abstract commands.
Warning: Reading is bugged for bursts of multiple words. The current fix is only reading a single word burst (see: https://github.com/7FM/riscv-openocd/commit/e5311996673686a466fecea7e49f248d602ba918). Write bursts are bugged too and cause duplicate writes at the end of each burst. This was mitigated by filtering out certain requests that triggered undesired write actions (see: https://github.com/7FM/riscv-openocd/commit/f189fd2c477f07386e062d75b7f8af6473919f34#). Both problems also occurred in CVA6. We therefore suspect, that there is a problem with the OpenOCD implementation for TaPaSCo.
