📚 Our team is a research group which applies Electronic Design Automation (EDA) techniques to Cyber-Physical Production Systems (CPPSs) and Industrial IoT (IIoT) for modeling, simulation, synthesis, and testing of production lines.
🏛 We are within the Department of Engineering of the University of Verona.
Home of the Unified Mixed-signal Netlist Parser Framework
HIF Core defines the abstract syntax tree (AST) and internal C++ representation for hardware descriptions, providing the foundation for front-end parsing and back-end code generation.
HIF Frontend translates various hardware description languages (HDLs) into HIF’s internal AST representation, enabling a unified intermediate format for analysis and transformation.
HIF Backend converts the internal AST representation into target hardware description languages (HDLs) and formats, facilitating seamless code generation and interoperability.
Official implementation of the paper "From Scratch to Twin: The Design of your First Human-Centric Digital Twin" accepted @ ISIE 2025.
Official implementation of the paper "Human-Centered Digital Twin for Industry 5.0" accepted @ DATE 2025.
Official implementation of the paper "GAIA: A Comprehensive Pipeline for Enabling Aircraft Digital Twin Creation" accepted @ ISIE 2025.
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