feat(drivers): port DP3246 shift driver initialization#129
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stuartparmenter wants to merge 1 commit into
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feat(drivers): port DP3246 shift driver initialization#129stuartparmenter wants to merge 1 commit into
stuartparmenter wants to merge 1 commit into
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Replaces the DP3246 stub (which logged a warning and did nothing) with the bit-bang init sequence: pre-clear sweep, REG1 (max output current, no OE widening), REG2 (max blanking potential, single-edge transfer, power-saving features off), trailing blank, OE enable. DP3246 also requires a rising-edge clock, so HUB75_CLK_PHASE_INVERTED now defaults on when DP3246 is selected (mirrors the MBI5124 default), and the dispatch case logs a warning if the flag was left false in code-constructed configs. Known limitation: DP3246 also expects LAT held high for 3 clocks per row at runtime. The DMA backends still emit a 1-cycle LAT pulse, so panels may show artifacts after a successful init. The Kconfig help text and a runtime ESP_LOGW make this explicit; widening the runtime LAT pulse is left to a follow-up. Internal helper shift_with_latch collapses the four near-identical "shift N pixels, latch the tail" sweeps in dp3246_init into a single parameterized call.
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Summary
DP3246stub (which logged"DP3246 initialization not yet implemented"and did nothing) with the actual bit-bang init sequence: pre-clear sweep → REG1 (max output current, no OE widening) → REG2 (max blanking potential, single-edge transfer, power-saving features off) → trailing blank → OE enable. New file:components/hub75/src/drivers/dp3246.cpp.HUB75_CLK_PHASE_INVERTEDnow alsodefault y if HUB75_DRIVER_DP3246(mirrors the MBI5124 default). For users who constructHub75Configdirectly in code, the dispatch inDriverInit::initializelogs a warning whenclk_phase_invertedis left false.shift_with_latch(pins, pixels_per_row, pattern, lat_cycles)collapses the four near-identical "shift N pixels, raise LAT for the last K, drop LAT" sweeps indp3246_initinto a single parameterized call. Latch widths are named (LAT_CYCLES_BLANK = 3,LAT_CYCLES_REG1 = 11,LAT_CYCLES_REG2 = 12).Known limitation (called out in code, log, and Kconfig help)
DP3246 also expects LAT held high for 3 clock cycles per row at runtime, not just during init. The DMA backends (
gdma_dma,i2s_dma,parlio_dma) currently emit a 1-cycle LAT pulse on the last word of each row, so panels may still show artifacts after this init succeeds. Widening the runtime LAT pulse is intentionally left to a follow-up PR — that change touches all three DMA backends and adds a newHub75Config::latch_pulse_widthfield, which is too much for an init-only port.Test plan
simple_colorsexample withCONFIG_HUB75_DRIVER_DP3246=yfor ESP32, ESP32-S2, ESP32-S3, ESP32-P4, ESP32-C6 — confirm no missing symbol / link errors and thatHUB75_CLK_PHASE_INVERTEDflips on automatically.casebranch; only addition is the conditionalclk_phase_invertedwarning).